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Daisuke Nojiria6712f32015-01-23 10:06:19 -08001##
2## This file is part of the coreboot project.
3##
4## Copyright 2014 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
Patrick Georgib890a122015-03-26 15:17:45 +010017## Foundation, Inc.
Daisuke Nojiria6712f32015-01-23 10:06:19 -080018##
19
20config SOC_BROADCOM_CYGNUS
21 bool
22 default n
23 select ARCH_BOOTBLOCK_ARMV7
24 select ARCH_RAMSTAGE_ARMV7
25 select ARCH_ROMSTAGE_ARMV7
26 select ARCH_VERSTAGE_ARMV7
27 select BOOTBLOCK_CONSOLE
Daisuke Nojiria6712f32015-01-23 10:06:19 -080028 select GENERIC_UDELAY
29 select HAVE_MONOTONIC_TIMER
Daisuke Nojiria6712f32015-01-23 10:06:19 -080030 select HAVE_UART_SPECIAL
Icarus Chaud5f551a2015-02-13 15:16:37 -080031 select HAS_PRECBMEM_TIMESTAMP_REGION
Stefan Reinauer97db1fb2015-03-26 15:58:41 -070032 select GENERIC_GPIO_LIB
Daisuke Nojiria6712f32015-01-23 10:06:19 -080033
34if SOC_BROADCOM_CYGNUS
35
Martin Roth967cd9a2015-08-18 14:22:58 -060036config CHROMEOS
37 select SEPARATE_VERSTAGE
38 select RETURN_FROM_VERSTAGE
39
Daisuke Nojiria6712f32015-01-23 10:06:19 -080040config BOOTBLOCK_CPU_INIT
41 string
42 default "soc/broadcom/cygnus/bootblock.c"
43
Daisuke Nojiric047b102015-01-23 10:02:24 -080044config CONSOLE_SERIAL_UART_ADDRESS
45 hex
Patrick Georgi01368ed2015-04-16 15:27:52 +020046 depends on DRIVERS_UART
Daisuke Nojiric047b102015-01-23 10:02:24 -080047 default 0x18023000
48
Icarus Chaud5f551a2015-02-13 15:16:37 -080049config CYGNUS_DDR800
50 bool "DDR Speed at 800MHz"
51 default y
52
Icarus Chaube476362015-04-07 16:09:24 -070053config CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE
54 bool "Enable DDR auto self-refresh"
55 default y
56 help
57 Warning: M0 expects that auto self-refresh is enabled. Modify
58 with caution.
59
60
Icarus Chaud5f551a2015-02-13 15:16:37 -080061config CYGNUS_SHMOO_REUSE_DDR_32BIT
62 bool "Indicate if DDR width is 32-bit"
63 default n
64
65config CYGNUS_SDRAM_TEST_DDR
66 bool "Run a write-read test on DDR after initialization"
67 default n
68
69config CYGNUS_PRINT_SHMOO_DEBUG
70 bool "Print debug info for shmoo"
71 default n
Icarus Chau98558952015-03-03 19:36:03 -080072
73config CYGNUS_GPIO_TEST
74 bool "Run a test on gpio"
75 default n
76
Daisuke Nojiria6712f32015-01-23 10:06:19 -080077endif