Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 1 | config SOC_INTEL_APOLLOLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Apollolake support |
| 5 | |
| 6 | if SOC_INTEL_APOLLOLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
Aaron Durbin | ed35b7c | 2016-07-13 23:17:38 -0500 | [diff] [blame] | 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 11 | select ARCH_BOOTBLOCK_X86_32 |
| 12 | select ARCH_RAMSTAGE_X86_32 |
| 13 | select ARCH_ROMSTAGE_X86_32 |
| 14 | select ARCH_VERSTAGE_X86_32 |
| 15 | # CPU specific options |
| 16 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| 17 | select IOAPIC |
| 18 | select SMP |
| 19 | select SSE2 |
| 20 | select SUPPORT_CPU_UCODE_IN_CBFS |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 21 | # Audio options |
| 22 | select ACPI_NHLT |
| 23 | select SOC_INTEL_COMMON_NHLT |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 24 | # Misc options |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 25 | select C_ENVIRONMENT_BOOTBLOCK |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 26 | select COLLECT_TIMESTAMPS |
Aaron Durbin | c3ee3f6 | 2016-05-11 10:35:49 -0500 | [diff] [blame] | 27 | select COMMON_FADT |
Duncan Laurie | d25dd99 | 2016-06-29 10:47:48 -0700 | [diff] [blame] | 28 | select GENERIC_GPIO_LIB |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 29 | select HAVE_INTEL_FIRMWARE |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 30 | select HAVE_SMI_HANDLER |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 31 | select MMCONF_SUPPORT |
| 32 | select MMCONF_SUPPORT_DEFAULT |
Aaron Durbin | f5ff854 | 2016-05-05 10:38:03 -0500 | [diff] [blame] | 33 | select NO_FIXED_XIP_ROM_SIZE |
Furquan Shaikh | 12a8aba | 2016-05-06 09:50:35 -0700 | [diff] [blame] | 34 | select NO_STAGE_CACHE |
Furquan Shaikh | 94b18a1 | 2016-05-04 23:25:16 -0700 | [diff] [blame] | 35 | select NO_XIP_EARLY_STAGES |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 36 | select PARALLEL_MP |
| 37 | select PCIEXP_ASPM |
| 38 | select PCIEXP_COMMON_CLOCK |
| 39 | select PCIEXP_CLK_PM |
| 40 | select PCIEXP_L1_SUB_STATE |
Aaron Durbin | eebe0e0 | 2016-03-18 11:19:38 -0500 | [diff] [blame] | 41 | select POSTCAR_STAGE |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 42 | select REG_SCRIPT |
| 43 | select RELOCATABLE_RAMSTAGE # Build fails if this is not selected |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 44 | select SMM_TSEG |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 45 | select SOC_INTEL_COMMON |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 46 | select SOC_INTEL_COMMON_ACPI |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 47 | select SOC_INTEL_COMMON_LPSS_I2C |
| 48 | select SOC_INTEL_COMMON_SMI |
Alexandru Gagniuc | 0581a67 | 2016-02-24 15:08:23 -0800 | [diff] [blame] | 49 | select SPI_FLASH |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 50 | select UDELAY_TSC |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 51 | select TSC_CONSTANT_RATE |
Hannah Williams | b13d454 | 2016-03-14 17:38:51 -0700 | [diff] [blame] | 52 | select TSC_MONOTONIC_TIMER |
| 53 | select HAVE_MONOTONIC_TIMER |
Andrey Petrov | 0d18791 | 2016-02-25 18:39:38 -0800 | [diff] [blame] | 54 | select PLATFORM_USES_FSP2_0 |
Zhao, Lijian | d8d42c2 | 2016-03-14 14:19:22 -0700 | [diff] [blame] | 55 | select HAVE_HARD_RESET |
| 56 | select SOC_INTEL_COMMON |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_GFX_OPREGION |
| 58 | select ADD_VBT_DATA_FILE |
Zhao, Lijian | d8d42c2 | 2016-03-14 14:19:22 -0700 | [diff] [blame] | 59 | |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 60 | config CHROMEOS |
| 61 | select CHROMEOS_RAMOOPS_DYNAMIC |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 62 | select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC |
| 63 | select SEPARATE_VERSTAGE |
| 64 | select VBOOT_OPROM_MATTERS |
Furquan Shaikh | 7c7b291 | 2016-07-22 09:02:35 -0700 | [diff] [blame] | 65 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 66 | select VBOOT_STARTS_IN_BOOTBLOCK |
Furquan Shaikh | 2a12e2e | 2016-07-25 11:48:03 -0700 | [diff] [blame] | 67 | select VBOOT_VBNV_CMOS |
| 68 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 69 | select VIRTUAL_DEV_SWITCH |
| 70 | |
Aaron Durbin | 80a3df2 | 2016-04-27 23:05:52 -0500 | [diff] [blame] | 71 | config TPM_ON_FAST_SPI |
| 72 | bool |
| 73 | default n |
| 74 | select LPC_TPM |
| 75 | help |
| 76 | TPM part is conntected on Fast SPI interface, but the LPC MMIO |
| 77 | TPM transactions are decoded and serialized over the SPI interface. |
| 78 | |
Zhao, Lijian | d8d42c2 | 2016-03-14 14:19:22 -0700 | [diff] [blame] | 79 | config SOC_INTEL_COMMON_RESET |
| 80 | bool |
Andrey Petrov | 9c0e180 | 2016-06-23 08:26:00 -0700 | [diff] [blame] | 81 | default y |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 82 | |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 83 | config MMCONF_BASE_ADDRESS |
| 84 | hex "PCI MMIO Base Address" |
| 85 | default 0xe0000000 |
| 86 | |
| 87 | config IOSF_BASE_ADDRESS |
| 88 | hex "MMIO Base Address of sideband bus" |
| 89 | default 0xd0000000 |
| 90 | |
| 91 | config DCACHE_RAM_BASE |
| 92 | hex "Base address of cache-as-RAM" |
| 93 | default 0xfef00000 |
| 94 | |
| 95 | config DCACHE_RAM_SIZE |
| 96 | hex "Length in bytes of cache-as-RAM" |
Andrey Petrov | 0e46307 | 2016-04-23 14:28:21 -0700 | [diff] [blame] | 97 | default 0x100000 |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 98 | help |
| 99 | The size of the cache-as-ram region required during bootblock |
| 100 | and/or romstage. |
| 101 | |
| 102 | config DCACHE_BSP_STACK_SIZE |
| 103 | hex |
| 104 | default 0x4000 |
| 105 | help |
| 106 | The amount of anticipated stack usage in CAR by bootblock and |
| 107 | other stages. |
| 108 | |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 109 | config CPU_ADDR_BITS |
| 110 | int |
| 111 | default 36 |
| 112 | |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 113 | config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ |
| 114 | depends on SOC_INTEL_COMMON_LPSS_I2C |
| 115 | int |
| 116 | default 133 |
| 117 | |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 118 | config CONSOLE_UART_BASE_ADDRESS |
| 119 | depends on CONSOLE_SERIAL |
| 120 | hex "MMIO base address for UART" |
| 121 | default 0xde000000 |
| 122 | |
Aaron Durbin | 6181030 | 2016-02-24 18:49:07 -0600 | [diff] [blame] | 123 | config SOC_UART_DEBUG |
| 124 | bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE." |
| 125 | default n |
| 126 | select CONSOLE_SERIAL |
| 127 | select BOOTBLOCK_CONSOLE |
| 128 | select DRIVERS_UART |
| 129 | select DRIVERS_UART_8250MEM_32 |
| 130 | select NO_UART_ON_SUPERIO |
| 131 | |
Aaron Durbin | ada13ed | 2016-02-11 14:47:33 -0600 | [diff] [blame] | 132 | # 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB. |
| 133 | config C_ENV_BOOTBLOCK_SIZE |
| 134 | hex |
| 135 | default 0x8000 |
| 136 | |
Andrey Petrov | 5672dcd | 2016-02-12 15:12:43 -0800 | [diff] [blame] | 137 | # This SoC does not map SPI flash like many previous SoC. Therefore we provide |
| 138 | # a custom media driver that facilitates mapping |
| 139 | config X86_TOP4G_BOOTMEDIA_MAP |
| 140 | bool |
| 141 | default n |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 142 | |
| 143 | config ROMSTAGE_ADDR |
| 144 | hex |
Andrey Petrov | 0e46307 | 2016-04-23 14:28:21 -0700 | [diff] [blame] | 145 | default 0xfef3e000 |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 146 | help |
| 147 | The base address (in CAR) where romstage should be linked |
| 148 | |
Aaron Durbin | bef75e7 | 2016-05-26 11:00:44 -0500 | [diff] [blame] | 149 | config VERSTAGE_ADDR |
| 150 | hex |
| 151 | default 0xfef60000 |
| 152 | help |
| 153 | The base address (in CAR) where verstage should be linked |
| 154 | |
Hannah Williams | b13d454 | 2016-03-14 17:38:51 -0700 | [diff] [blame] | 155 | config CACHE_MRC_SETTINGS |
| 156 | bool |
| 157 | default y |
| 158 | |
Andrey Petrov | 79091db7 | 2016-05-17 00:03:27 -0700 | [diff] [blame] | 159 | config FSP_M_ADDR |
| 160 | hex |
| 161 | default 0xfef60000 |
| 162 | help |
| 163 | The address FSP-M will be relocated to during build time |
| 164 | |
Aaron Durbin | 9f444c3 | 2016-05-20 10:48:44 -0500 | [diff] [blame] | 165 | config NEED_LBP2 |
| 166 | bool "Write contents for logical boot partition 2." |
| 167 | default n |
| 168 | help |
| 169 | Write the contents from a file into the logical boot partition 2 |
| 170 | region defined by LBP2_FMAP_NAME. |
| 171 | |
| 172 | config LBP2_FMAP_NAME |
| 173 | string "Name of FMAP region to put logical boot partition 2" |
| 174 | depends on NEED_LBP2 |
| 175 | default "SIGN_CSE" |
| 176 | help |
| 177 | Name of FMAP region to write logical boot partition 2 data. |
| 178 | |
| 179 | config LBP2_FILE_NAME |
| 180 | string "Path of file to write to logical boot partition 2 region" |
| 181 | depends on NEED_LBP2 |
| 182 | default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/lbp2.bin" |
| 183 | help |
| 184 | Name of file to store in the logical boot partition 2 region. |
| 185 | |
Furquan Shaikh | 7043bf3 | 2016-05-28 12:57:05 -0700 | [diff] [blame] | 186 | config NEED_IFWI |
| 187 | bool "Write content into IFWI region" |
| 188 | default n |
| 189 | help |
| 190 | Write the content from a file into IFWI region defined by |
| 191 | IFWI_FMAP_NAME. |
| 192 | |
| 193 | config IFWI_FMAP_NAME |
| 194 | string "Name of FMAP region to pull IFWI into" |
| 195 | depends on NEED_IFWI |
| 196 | default "IFWI" |
| 197 | help |
| 198 | Name of FMAP region to write IFWI. |
| 199 | |
| 200 | config IFWI_FILE_NAME |
| 201 | string "Path of file to write to IFWI region" |
| 202 | depends on NEED_IFWI |
| 203 | default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin" |
| 204 | help |
| 205 | Name of file to store in the IFWI region. |
| 206 | |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 207 | config NHLT_DMIC_2CH_16B |
| 208 | bool |
| 209 | depends on ACPI_NHLT |
| 210 | default n |
| 211 | help |
| 212 | Include DSP firmware settings for 2 channel 16B DMIC array. |
| 213 | |
| 214 | config NHLT_MAX98357 |
| 215 | bool |
| 216 | depends on ACPI_NHLT |
| 217 | default n |
| 218 | help |
| 219 | Include DSP firmware settings for headset codec. |
| 220 | |
| 221 | config NHLT_DA7219 |
| 222 | bool |
| 223 | depends on ACPI_NHLT |
| 224 | default n |
| 225 | help |
| 226 | Include DSP firmware settings for headset codec. |
| 227 | |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 228 | endif |