Ed Swierk | 62eee3f | 2008-03-16 23:31:04 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Arastra, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Ed Swierk | 62eee3f | 2008-03-16 23:31:04 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Edward O'Callaghan | e64f5b1 | 2015-01-04 04:25:38 +1100 | [diff] [blame] | 17 | #ifndef SUPERIO_INTEL_I3100_H |
| 18 | #define SUPERIO_INTEL_I3100_H |
Uwe Hermann | 7fa0819 | 2010-11-08 20:55:24 +0000 | [diff] [blame] | 19 | |
Uwe Hermann | 7d34188 | 2010-11-05 00:07:13 +0000 | [diff] [blame] | 20 | /* |
| 21 | * Datasheet: |
| 22 | * - Name: Intel 3100 Chipset |
| 23 | * - URL: http://www.intel.com/design/intarch/datashts/313458.htm |
| 24 | * - PDF: http://download.intel.com/design/intarch/datashts/31345803.pdf |
| 25 | * - Revision / Date: 007, October 2008 |
| 26 | * - Order number: 313458-007US |
| 27 | */ |
Ed Swierk | 62eee3f | 2008-03-16 23:31:04 +0000 | [diff] [blame] | 28 | |
Uwe Hermann | 7d34188 | 2010-11-05 00:07:13 +0000 | [diff] [blame] | 29 | /* |
| 30 | * The SIW ("Serial I/O and Watchdog Timer") integrated into the i3100 is |
| 31 | * very similar to a Super I/O, both in functionality and config mechanism. |
| 32 | * |
| 33 | * The SIW contains: |
| 34 | * - UART(s) |
| 35 | * - Serial interrupt controller |
| 36 | * - Watchdog timer (WDT) |
| 37 | * - LPC interface |
| 38 | */ |
| 39 | |
| 40 | /* Logical device numbers (LDNs). */ |
Ed Swierk | 62eee3f | 2008-03-16 23:31:04 +0000 | [diff] [blame] | 41 | #define I3100_SP1 0x04 /* Com1 */ |
| 42 | #define I3100_SP2 0x05 /* Com2 */ |
| 43 | #define I3100_WDT 0x06 /* Watchdog timer */ |
| 44 | |
Uwe Hermann | d1a1d57 | 2010-11-10 18:22:11 +0000 | [diff] [blame] | 45 | /* Registers and bit definitions: */ |
| 46 | |
| 47 | #define I3100_SIW_CONFIGURATION 0x29 |
| 48 | |
| 49 | /* |
| 50 | * SIW_CONFIGURATION[3:2] = UART_CLK predivide |
| 51 | * 00: divide by 1 |
| 52 | * 01: divide by 8 |
| 53 | * 10: divide by 26 |
| 54 | * 11: reserved |
| 55 | */ |
| 56 | #define I3100_UART_CLK_PREDIVIDE_1 0x00 |
| 57 | #define I3100_UART_CLK_PREDIVIDE_8 0x01 |
| 58 | #define I3100_UART_CLK_PREDIVIDE_26 0x02 |
Ed Swierk | b8e53eb | 2008-10-13 23:18:56 +0000 | [diff] [blame] | 59 | |
Edward O'Callaghan | e64f5b1 | 2015-01-04 04:25:38 +1100 | [diff] [blame] | 60 | #include <arch/io.h> |
| 61 | #include <stdint.h> |
| 62 | |
| 63 | void i3100_configure_uart_clk(pnp_devfn_t dev, u8 predivide); |
| 64 | void i3100_enable_serial(pnp_devfn_t dev, u16 iobase); |
| 65 | |
| 66 | #endif /* SUPERIO_INTEL_I3100_H */ |