Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 secunet Security Networks AG |
| 5 | * (Written by Nico Huber <nico.huber@secunet.com> for secunet) |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <arch/io.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
| 22 | |
| 23 | #include "i82801ix.h" |
| 24 | |
| 25 | static void thermal_init(struct device *dev) |
| 26 | { |
| 27 | if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) |
| 28 | return; |
| 29 | |
| 30 | u8 reg8; |
| 31 | u32 reg32; |
| 32 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 33 | pci_write_config32(dev, 0x10, (uintptr_t)DEFAULT_TBAR); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 34 | reg32 = pci_read_config32(dev, 0x04); |
| 35 | pci_write_config32(dev, 0x04, reg32 | (1 << 1)); |
| 36 | |
| 37 | write32(DEFAULT_TBAR + 0x04, 0); /* Clear thermal trip points. */ |
| 38 | write32(DEFAULT_TBAR + 0x44, 0); |
| 39 | |
| 40 | write8(DEFAULT_TBAR + 0x01, 0xba); /* Enable sensor 0 + 1. */ |
| 41 | write8(DEFAULT_TBAR + 0x41, 0xba); |
| 42 | |
| 43 | reg8 = read8(DEFAULT_TBAR + 0x08); /* Lock thermal registers. */ |
| 44 | write8(DEFAULT_TBAR + 0x08, reg8 | (1 << 7)); |
| 45 | reg8 = read8(DEFAULT_TBAR + 0x48); |
| 46 | write8(DEFAULT_TBAR + 0x48, reg8 | (1 << 7)); |
| 47 | |
| 48 | reg32 = pci_read_config32(dev, 0x04); |
| 49 | pci_write_config32(dev, 0x04, reg32 & ~(1 << 1)); |
| 50 | pci_write_config32(dev, 0x10, 0); |
| 51 | } |
| 52 | |
| 53 | static void thermal_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 54 | { |
| 55 | if (!vendor || !device) { |
| 56 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 57 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 58 | } else { |
| 59 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 60 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 61 | } |
| 62 | } |
| 63 | |
| 64 | static struct pci_operations thermal_pci_ops = { |
| 65 | .set_subsystem = thermal_set_subsystem, |
| 66 | }; |
| 67 | |
| 68 | static struct device_operations device_ops = { |
| 69 | .read_resources = pci_dev_read_resources, |
| 70 | .set_resources = pci_dev_set_resources, |
| 71 | .enable_resources = pci_dev_enable_resources, |
| 72 | .init = thermal_init, |
| 73 | .scan_bus = 0, |
| 74 | .ops_pci = &thermal_pci_ops, |
| 75 | }; |
| 76 | |
| 77 | static const struct pci_driver ich9_thermal __pci_driver = { |
| 78 | .ops = &device_ops, |
| 79 | .vendor = PCI_VENDOR_ID_INTEL, |
| 80 | .device = 0x2932, |
| 81 | }; |