Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 4 | * Copyright (C) 2008-2009 coresystems GmbH |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 5 | * |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pci_ids.h> |
| 21 | #include "i82801gx.h" |
| 22 | |
| 23 | typedef struct southbridge_intel_i82801gx_config config_t; |
| 24 | |
| 25 | static void sata_init(struct device *dev) |
| 26 | { |
| 27 | u32 reg32; |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 28 | u16 reg16; |
Sven Schnelle | b2f173e | 2011-10-27 13:05:40 +0200 | [diff] [blame] | 29 | u32 *ahci_bar; |
| 30 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 31 | /* Get the chip configuration */ |
| 32 | config_t *config = dev->chip_info; |
| 33 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 34 | printk(BIOS_DEBUG, "i82801gx_sata: initializing...\n"); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 35 | |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 36 | if (config == NULL) { |
Uwe Hermann | 607614d | 2010-11-18 20:12:13 +0000 | [diff] [blame] | 37 | printk(BIOS_ERR, "i82801gx_sata: error: device not in devicetree.cb!\n"); |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 38 | return; |
| 39 | } |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 40 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 41 | /* SATA configuration */ |
| 42 | |
| 43 | /* Enable BARs */ |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 44 | pci_write_config16(dev, PCI_COMMAND, 0x0007); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 45 | |
| 46 | if (config->ide_legacy_combined) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 47 | printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 48 | /* No AHCI: clear AHCI base */ |
| 49 | pci_write_config32(dev, 0x24, 0x00000000); |
| 50 | /* And without AHCI BAR no memory decoding */ |
| 51 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 52 | reg16 &= ~PCI_COMMAND_MEMORY; |
| 53 | pci_write_config16(dev, PCI_COMMAND, reg16); |
| 54 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 55 | pci_write_config8(dev, 0x09, 0x80); |
| 56 | |
| 57 | /* Set timings */ |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 58 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 59 | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); |
| 60 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 61 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 62 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 63 | |
| 64 | /* Sync DMA */ |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 65 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); |
| 66 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 67 | |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 68 | /* Set IDE I/O Configuration */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 69 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 70 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 71 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 72 | /* Combine IDE - SATA configuration */ |
| 73 | pci_write_config8(dev, 0x90, 0x02); |
| 74 | |
| 75 | /* Port 0 & 1 enable */ |
| 76 | pci_write_config8(dev, 0x92, 0x0f); |
| 77 | |
| 78 | /* SATA Initialization register */ |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 79 | pci_write_config32(dev, 0x94, 0x5a000180); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 80 | } else if(config->sata_ahci) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 81 | printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 82 | /* Allow both Legacy and Native mode */ |
| 83 | pci_write_config8(dev, 0x09, 0x8f); |
| 84 | |
| 85 | /* Set Interrupt Line */ |
| 86 | /* Interrupt Pin is set by D31IP.PIP */ |
| 87 | pci_write_config8(dev, INTR_LN, 0x0a); |
| 88 | |
| 89 | /* Set timings */ |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 90 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 91 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 92 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 93 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 94 | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 95 | |
| 96 | /* Sync DMA */ |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 97 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); |
| 98 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 99 | |
| 100 | /* Set IDE I/O Configuration */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 101 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 102 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 103 | |
| 104 | /* Set Sata Controller Mode. */ |
Bernhard M. Wiedermann | 6769396 | 2010-04-22 22:47:29 +0000 | [diff] [blame] | 105 | pci_write_config8(dev, 0x90, 0x40); // 40=AHCI |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 106 | |
Sven Schnelle | b2f173e | 2011-10-27 13:05:40 +0200 | [diff] [blame] | 107 | /* In ACHI mode, bit[3:0] must always be set |
| 108 | * (Port status is controlled through AHCI BAR) |
| 109 | */ |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 110 | pci_write_config8(dev, 0x92, 0x0f); |
| 111 | |
Sven Schnelle | b2f173e | 2011-10-27 13:05:40 +0200 | [diff] [blame] | 112 | ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff); |
| 113 | ahci_bar[3] = config->sata_ports_implemented; |
| 114 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 115 | /* SATA Initialization register */ |
| 116 | pci_write_config32(dev, 0x94, 0x1a000180); |
| 117 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 118 | printk(BIOS_DEBUG, "SATA controller in plain mode.\n"); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 119 | /* Set Sata Controller Mode. No Mapping(?) */ |
| 120 | pci_write_config8(dev, 0x90, 0x00); |
| 121 | |
| 122 | /* No AHCI: clear AHCI base */ |
| 123 | pci_write_config32(dev, 0x24, 0x00000000); |
| 124 | |
| 125 | /* And without AHCI BAR no memory decoding */ |
| 126 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 127 | reg16 &= ~PCI_COMMAND_MEMORY; |
| 128 | pci_write_config16(dev, PCI_COMMAND, reg16); |
| 129 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 130 | /* Native mode capable on both primary and secondary (0xa) |
| 131 | * or'ed with enabled (0x50) = 0xf |
| 132 | */ |
| 133 | pci_write_config8(dev, 0x09, 0x8f); |
| 134 | |
| 135 | /* Set Interrupt Line */ |
| 136 | /* Interrupt Pin is set by D31IP.PIP */ |
| 137 | pci_write_config8(dev, INTR_LN, 0xff); |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 138 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 139 | /* Set timings */ |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 140 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 141 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 142 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 143 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 144 | IDE_SITRE | IDE_ISP_3_CLOCKS | |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 145 | IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 146 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 147 | /* Sync DMA */ |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 148 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); |
| 149 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 150 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 151 | /* Set IDE I/O Configuration */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 152 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 153 | pci_write_config32(dev, IDE_CONFIG, reg32); |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 154 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 155 | /* Port 0 & 1 enable XXX */ |
| 156 | pci_write_config8(dev, 0x92, 0x15); |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 157 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 158 | /* SATA Initialization register */ |
| 159 | pci_write_config32(dev, 0x94, 0x1a000180); |
| 160 | } |
| 161 | |
| 162 | /* All configurations need this SATA initialization sequence */ |
| 163 | pci_write_config8(dev, 0xa0, 0x40); |
| 164 | pci_write_config8(dev, 0xa6, 0x22); |
| 165 | pci_write_config8(dev, 0xa0, 0x78); |
| 166 | pci_write_config8(dev, 0xa6, 0x22); |
| 167 | pci_write_config8(dev, 0xa0, 0x88); |
| 168 | reg32 = pci_read_config32(dev, 0xa4); |
| 169 | reg32 &= 0xc0c0c0c0; |
| 170 | reg32 |= 0x1b1b1212; |
| 171 | pci_write_config32(dev, 0xa4, reg32); |
| 172 | pci_write_config8(dev, 0xa0, 0x8c); |
| 173 | reg32 = pci_read_config32(dev, 0xa4); |
| 174 | reg32 &= 0xc0c0ff00; |
| 175 | reg32 |= 0x121200aa; |
| 176 | pci_write_config32(dev, 0xa4, reg32); |
| 177 | pci_write_config8(dev, 0xa0, 0x00); |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 178 | |
| 179 | pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 180 | |
| 181 | /* Sata Initialization Register */ |
| 182 | reg32 = pci_read_config32(dev, 0x94); |
| 183 | reg32 |= (1 << 30); // due to some bug |
| 184 | pci_write_config32(dev, 0x94, reg32); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 185 | } |
| 186 | |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 187 | static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 188 | { |
| 189 | if (!vendor || !device) { |
| 190 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 191 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 192 | } else { |
| 193 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 194 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 195 | } |
| 196 | } |
| 197 | |
| 198 | static struct pci_operations sata_pci_ops = { |
| 199 | .set_subsystem = sata_set_subsystem, |
| 200 | }; |
| 201 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 202 | static struct device_operations sata_ops = { |
| 203 | .read_resources = pci_dev_read_resources, |
| 204 | .set_resources = pci_dev_set_resources, |
| 205 | .enable_resources = pci_dev_enable_resources, |
| 206 | .init = sata_init, |
| 207 | .scan_bus = 0, |
| 208 | .enable = i82801gx_enable, |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 209 | .ops_pci = &sata_pci_ops, |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 210 | }; |
| 211 | |
Patrick Georgi | efff733 | 2012-07-26 19:48:23 +0200 | [diff] [blame] | 212 | static const unsigned short sata_ids[] = { |
| 213 | 0x27c0, /* Desktop Non-AHCI and Non-RAID Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ |
| 214 | 0x27c4, /* Mobile Non-AHCI and Non-RAID Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */ |
| 215 | /* NOTE: Any of the below are not properly supported yet. */ |
| 216 | 0x27c1, /* Desktop AHCI Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ |
| 217 | 0x27c3, /* Desktop RAID mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ |
| 218 | 0x27c5, /* Mobile AHCI Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */ |
| 219 | 0x27c6, /* ICH7M DH Raid Mode: 82801GHM (ICH7-M DH) */ |
| 220 | 0 |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 221 | }; |
| 222 | |
Patrick Georgi | efff733 | 2012-07-26 19:48:23 +0200 | [diff] [blame] | 223 | static const struct pci_driver i82801gx_sata_driver __pci_driver = { |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 224 | .ops = &sata_ops, |
| 225 | .vendor = PCI_VENDOR_ID_INTEL, |
Patrick Georgi | efff733 | 2012-07-26 19:48:23 +0200 | [diff] [blame] | 226 | .devices= sata_ids, |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 227 | }; |