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Stefan Reinauerdebb11f2008-10-29 04:46:52 +00001/*
2 * This file is part of the coreboot project.
3 *
Stefan Reinauer54309d62009-01-20 22:53:10 +00004 * Copyright (C) 2008-2009 coresystems GmbH
Stefan Reinauerdebb11f2008-10-29 04:46:52 +00005 *
Stefan Reinauera8e11682009-03-11 14:54:18 +00006 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000010 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000015 */
16
17#include <console/console.h>
18#include <device/device.h>
19#include <device/pci.h>
20#include <device/pci_ids.h>
21#include <pc80/mc146818rtc.h>
22#include <pc80/isa-dma.h>
Stefan Reinauer54309d62009-01-20 22:53:10 +000023#include <pc80/i8259.h>
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000024#include <arch/io.h>
Uwe Hermann74d1a6e2010-10-12 17:34:08 +000025#include <arch/ioapic.h>
Stefan Reinauerab872542011-10-14 15:18:29 -070026#include <arch/acpi.h>
Stefan Reinauercadc5452010-12-18 23:29:37 +000027#include <cpu/cpu.h>
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000028#include "i82801gx.h"
Sven Schnellef4dc1a72011-06-05 11:33:41 +020029#include <cpu/x86/smm.h>
Vladimir Serbinenko0e646172014-08-31 00:27:05 +020030#include <arch/acpigen.h>
Vladimir Serbinenkod5d94ea2014-10-18 02:13:11 +020031#include <arch/smp/mpspec.h>
Vladimir Serbinenko0e646172014-08-31 00:27:05 +020032#include <cbmem.h>
33#include <string.h>
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010034#include <drivers/intel/gma/i915.h>
Vladimir Serbinenko0e646172014-08-31 00:27:05 +020035#include "nvs.h"
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000036
Stefan Reinauer573f7d42009-07-21 21:50:34 +000037#define NMI_OFF 0
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000038
Stefan Reinauer573f7d42009-07-21 21:50:34 +000039#define ENABLE_ACPI_MODE_IN_COREBOOT 0
40#define TEST_SMM_FLASH_LOCKDOWN 0
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000041
Stefan Reinauer54309d62009-01-20 22:53:10 +000042typedef struct southbridge_intel_i82801gx_config config_t;
43
Paul Menzelddddf152013-04-23 14:40:23 +020044/**
45 * Set miscellanous static southbridge features.
46 *
47 * @param dev PCI device with I/O APIC control registers
48 */
49static void i82801gx_enable_ioapic(struct device *dev)
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000050{
Paul Menzelddddf152013-04-23 14:40:23 +020051 /* Enable ACPI I/O range decode */
Kyösti Mälkki1cca3402013-02-26 19:21:39 +020052 pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000053
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080054 set_ioapic_id(VIO_APIC_VADDR, 0x02);
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000055
Paul Menzelddddf152013-04-23 14:40:23 +020056 /*
57 * Select Boot Configuration register (0x03) and
58 * use Processor System Bus (0x01) to deliver interrupts.
59 */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080060 io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000061}
62
63static void i82801gx_enable_serial_irqs(struct device *dev)
64{
65 /* Set packet length and toggle silent mode bit for one frame. */
66 pci_write_config8(dev, SERIRQ_CNTL,
67 (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
68}
69
Stefan Reinauer573f7d42009-07-21 21:50:34 +000070/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
71 * 0x00 - 0000 = Reserved
72 * 0x01 - 0001 = Reserved
73 * 0x02 - 0010 = Reserved
74 * 0x03 - 0011 = IRQ3
75 * 0x04 - 0100 = IRQ4
76 * 0x05 - 0101 = IRQ5
77 * 0x06 - 0110 = IRQ6
78 * 0x07 - 0111 = IRQ7
79 * 0x08 - 1000 = Reserved
80 * 0x09 - 1001 = IRQ9
81 * 0x0A - 1010 = IRQ10
82 * 0x0B - 1011 = IRQ11
83 * 0x0C - 1100 = IRQ12
84 * 0x0D - 1101 = Reserved
85 * 0x0E - 1110 = IRQ14
86 * 0x0F - 1111 = IRQ15
87 * PIRQ[n]_ROUT[7] - PIRQ Routing Control
88 * 0x80 - The PIRQ is not routed.
89 */
90
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000091static void i82801gx_pirq_init(device_t dev)
92{
Stefan Reinauer54309d62009-01-20 22:53:10 +000093 device_t irq_dev;
94 /* Get the chip configuration */
95 config_t *config = dev->chip_info;
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000096
Stefan Reinauer54309d62009-01-20 22:53:10 +000097 pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
98 pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
99 pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
100 pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
101
102 pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
103 pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
104 pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
105 pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
106
107 /* Eric Biederman once said we should let the OS do this.
108 * I am not so sure anymore he was right.
109 */
110
111 for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
112 u8 int_pin=0, int_line=0;
113
114 if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
115 continue;
116
117 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
118
119 switch (int_pin) {
120 case 1: /* INTA# */ int_line = config->pirqa_routing; break;
121 case 2: /* INTB# */ int_line = config->pirqb_routing; break;
122 case 3: /* INTC# */ int_line = config->pirqc_routing; break;
123 case 4: /* INTD# */ int_line = config->pirqd_routing; break;
124 }
125
126 if (!int_line)
127 continue;
128
129 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
130 }
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000131}
132
Stefan Reinauera8e11682009-03-11 14:54:18 +0000133static void i82801gx_gpi_routing(device_t dev)
134{
135 /* Get the chip configuration */
136 config_t *config = dev->chip_info;
137 u32 reg32 = 0;
138
139 /* An array would be much nicer here, or some
140 * other method of doing this.
141 */
142 reg32 |= (config->gpi0_routing & 0x03) << 0;
143 reg32 |= (config->gpi1_routing & 0x03) << 2;
144 reg32 |= (config->gpi2_routing & 0x03) << 4;
145 reg32 |= (config->gpi3_routing & 0x03) << 6;
146 reg32 |= (config->gpi4_routing & 0x03) << 8;
147 reg32 |= (config->gpi5_routing & 0x03) << 10;
148 reg32 |= (config->gpi6_routing & 0x03) << 12;
149 reg32 |= (config->gpi7_routing & 0x03) << 14;
150 reg32 |= (config->gpi8_routing & 0x03) << 16;
151 reg32 |= (config->gpi9_routing & 0x03) << 18;
152 reg32 |= (config->gpi10_routing & 0x03) << 20;
153 reg32 |= (config->gpi11_routing & 0x03) << 22;
154 reg32 |= (config->gpi12_routing & 0x03) << 24;
155 reg32 |= (config->gpi13_routing & 0x03) << 26;
156 reg32 |= (config->gpi14_routing & 0x03) << 28;
157 reg32 |= (config->gpi15_routing & 0x03) << 30;
158
Kyösti Mälkkib85a87b2014-12-29 11:32:27 +0200159 pci_write_config32(dev, GPIO_ROUT, reg32);
Stefan Reinauera8e11682009-03-11 14:54:18 +0000160}
161
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000162static void i82801gx_power_options(device_t dev)
163{
164 u8 reg8;
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000165 u16 reg16, pmbase;
166 u32 reg32;
Stefan Reinauer7a3d0952010-01-17 13:49:07 +0000167 const char *state;
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000168 /* Get the chip configuration */
169 config_t *config = dev->chip_info;
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000170
Stefan Reinauer08670622009-06-30 15:17:49 +0000171 int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
Luc Verhaegena9c5ea02009-06-03 14:19:33 +0000172 int nmi_option;
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000173
174 /* Which state do we want to goto after g3 (power restored)?
175 * 0 == S0 Full On
176 * 1 == S5 Soft Off
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000177 *
178 * If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000179 */
Varad Gautam06ef0462015-03-11 09:54:41 +0530180 pwr_on = MAINBOARD_POWER_ON;
181 get_option(&pwr_on, "power_on_after_fail");
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000182
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000183 reg8 = pci_read_config8(dev, GEN_PMCON_3);
184 reg8 &= 0xfe;
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000185 switch (pwr_on) {
186 case MAINBOARD_POWER_OFF:
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000187 reg8 |= 1;
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000188 state = "off";
189 break;
190 case MAINBOARD_POWER_ON:
191 reg8 &= ~1;
192 state = "on";
193 break;
194 case MAINBOARD_POWER_KEEP:
195 reg8 &= ~1;
196 state = "state keep";
197 break;
198 default:
199 state = "undefined";
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000200 }
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000201
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000202 reg8 |= (3 << 4); /* avoid #S4 assertions */
Stefan Reinauera8e11682009-03-11 14:54:18 +0000203 reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000204
205 pci_write_config8(dev, GEN_PMCON_3, reg8);
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000206 printk(BIOS_INFO, "Set power %s after power failure.\n", state);
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000207
208 /* Set up NMI on errors. */
209 reg8 = inb(0x61);
210 reg8 &= 0x0f; /* Higher Nibble must be 0 */
211 reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
212 // reg8 &= ~(1 << 2); /* PCI SERR# Enable */
213 reg8 |= (1 << 2); /* PCI SERR# Disable for now */
214 outb(reg8, 0x61);
215
216 reg8 = inb(0x70);
217 nmi_option = NMI_OFF;
Luc Verhaegena9c5ea02009-06-03 14:19:33 +0000218 get_option(&nmi_option, "nmi");
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000219 if (nmi_option) {
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000220 printk(BIOS_INFO, "NMI sources enabled.\n");
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000221 reg8 &= ~(1 << 7); /* Set NMI. */
222 } else {
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000223 printk(BIOS_INFO, "NMI sources disabled.\n");
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000224 reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
225 }
226 outb(reg8, 0x70);
227
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000228 /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000229 reg16 = pci_read_config16(dev, GEN_PMCON_1);
Stefan Reinauer7a3d0952010-01-17 13:49:07 +0000230 reg16 &= ~(3 << 0); // SMI# rate 1 minute
231 reg16 |= (1 << 2); // CLKRUN_EN - Mobile/Ultra only
232 reg16 |= (1 << 3); // Speedstep Enable - Mobile/Ultra only
233 reg16 |= (1 << 5); // CPUSLP_EN Desktop only
Sven Schnelle906f9ae2011-10-23 16:35:01 +0200234
235 if (config->c4onc3_enable)
236 reg16 |= (1 << 7);
237
Stefan Reinauer7a3d0952010-01-17 13:49:07 +0000238 // another laptop wants this?
239 // reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
240 reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000241#if DEBUG_PERIODIC_SMIS
242 /* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using
243 * periodic SMIs.
244 */
245 reg16 |= (3 << 0); // Periodic SMI every 8s
246#endif
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000247 pci_write_config16(dev, GEN_PMCON_1, reg16);
248
Stefan Reinauera8e11682009-03-11 14:54:18 +0000249 // Set the board's GPI routing.
250 i82801gx_gpi_routing(dev);
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000251
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000252 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000253
254 outl(config->gpe0_en, pmbase + GPE0_EN);
255 outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
256
257 /* Set up power management block and determine sleep mode */
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000258 reg32 = inl(pmbase + 0x04); // PM1_CNT
Stefan Reinauer7a3d0952010-01-17 13:49:07 +0000259
260 reg32 &= ~(7 << 10); // SLP_TYP
261 reg32 |= (1 << 1); // enable C3->C0 transition on bus master
262 reg32 |= (1 << 0); // SCI_EN
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000263 outl(reg32, pmbase + 0x04);
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000264}
265
Stefan Reinauera8e11682009-03-11 14:54:18 +0000266static void i82801gx_configure_cstates(device_t dev)
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000267{
268 u8 reg8;
Stefan Reinauer109ab312009-08-12 16:08:05 +0000269
Stefan Reinauera8e11682009-03-11 14:54:18 +0000270 reg8 = pci_read_config8(dev, 0xa9); // Cx state configuration
271 reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown
272 pci_write_config8(dev, 0xa9, reg8);
273
274 // Set Deeper Sleep configuration to recommended values
275 reg8 = pci_read_config8(dev, 0xaa);
276 reg8 &= 0xf0;
277 reg8 |= (2 << 2); // Deeper Sleep to Stop CPU: 34-40us
278 reg8 |= (2 << 0); // Deeper Sleep to Sleep: 15us
279 pci_write_config8(dev, 0xaa, reg8);
280}
281
282static void i82801gx_rtc_init(struct device *dev)
283{
284 u8 reg8;
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000285 int rtc_failed;
286
287 reg8 = pci_read_config8(dev, GEN_PMCON_3);
288 rtc_failed = reg8 & RTC_BATTERY_DEAD;
289 if (rtc_failed) {
290 reg8 &= ~RTC_BATTERY_DEAD;
291 pci_write_config8(dev, GEN_PMCON_3, reg8);
292 }
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000293 printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000294
Gabe Blackb3f08c62014-04-30 17:12:25 -0700295 cmos_init(rtc_failed);
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000296}
297
Stefan Reinauera8e11682009-03-11 14:54:18 +0000298static void enable_hpet(void)
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000299{
Stefan Reinauera8e11682009-03-11 14:54:18 +0000300 u32 reg32;
Stefan Reinauer109ab312009-08-12 16:08:05 +0000301
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000302 /* Move HPET to default address 0xfed00000 and enable it */
Stefan Reinauer7a3d0952010-01-17 13:49:07 +0000303 reg32 = RCBA32(HPTC);
Stefan Reinauera8e11682009-03-11 14:54:18 +0000304 reg32 |= (1 << 7); // HPET Address Enable
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000305 reg32 &= ~(3 << 0);
Stefan Reinauer7a3d0952010-01-17 13:49:07 +0000306 RCBA32(HPTC) = reg32;
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000307}
308
Stefan Reinauera8e11682009-03-11 14:54:18 +0000309static void enable_clock_gating(void)
310{
311 u32 reg32;
Stefan Reinauer109ab312009-08-12 16:08:05 +0000312
Stefan Reinauera8e11682009-03-11 14:54:18 +0000313 /* Enable Clock Gating for most devices */
Stefan Reinauer7a3d0952010-01-17 13:49:07 +0000314 reg32 = RCBA32(CG);
Stefan Reinauera8e11682009-03-11 14:54:18 +0000315 reg32 |= (1 << 31); // LPC clock gating
316 reg32 |= (1 << 30); // PATA clock gating
317 // SATA clock gating
318 reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
319 reg32 |= (1 << 23); // AC97 clock gating
Stefan Reinauer7a3d0952010-01-17 13:49:07 +0000320 reg32 |= (1 << 19); // USB EHCI clock gating
Stefan Reinauera8e11682009-03-11 14:54:18 +0000321 reg32 |= (1 << 3) | (1 << 1); // DMI clock gating
322 reg32 |= (1 << 2); // PCIe clock gating;
Stefan Reinauer7a3d0952010-01-17 13:49:07 +0000323 reg32 &= ~(1 << 20); // No static clock gating for USB
324 reg32 &= ~( (1 << 29) | (1 << 28) ); // Disable UHCI clock gating
325 RCBA32(CG) = reg32;
Stefan Reinauera8e11682009-03-11 14:54:18 +0000326}
Stefan Reinauer269563a2009-01-19 21:20:22 +0000327
Stefan Reinauer08670622009-06-30 15:17:49 +0000328#if CONFIG_HAVE_SMI_HANDLER
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000329static void i82801gx_lock_smm(struct device *dev)
330{
Stefan Reinauera8e11682009-03-11 14:54:18 +0000331#if TEST_SMM_FLASH_LOCKDOWN
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000332 u8 reg8;
Stefan Reinauera8e11682009-03-11 14:54:18 +0000333#endif
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000334
Kyösti Mälkkic3ed8862014-06-19 19:50:51 +0300335 if (!acpi_is_wakeup_s3()) {
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000336#if ENABLE_ACPI_MODE_IN_COREBOOT
Sven Schnellef4dc1a72011-06-05 11:33:41 +0200337 printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
338 outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
339 printk(BIOS_DEBUG, "done.\n");
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000340#else
Sven Schnellef4dc1a72011-06-05 11:33:41 +0200341 printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
342 outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
343 printk(BIOS_DEBUG, "done.\n");
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000344#endif
Sven Schnellee2618072011-06-05 11:39:12 +0200345 } else {
346 printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n");
347 outb(APM_CNT_ACPI_ENABLE, APM_CNT);
348 }
Stefan Reinauer109ab312009-08-12 16:08:05 +0000349 /* Don't allow evil boot loaders, kernels, or
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000350 * userspace applications to deceive us:
351 */
352 smm_lock();
353
354#if TEST_SMM_FLASH_LOCKDOWN
355 /* Now try this: */
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000356 printk(BIOS_DEBUG, "Locking BIOS to RO... ");
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000357 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000358 printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000359 (reg8&1)?"rw":"ro");
360 reg8 &= ~(1 << 0); /* clear BIOSWE */
361 pci_write_config8(dev, 0xdc, reg8);
362 reg8 |= (1 << 1); /* set BLE */
363 pci_write_config8(dev, 0xdc, reg8);
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000364 printk(BIOS_DEBUG, "ok.\n");
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000365 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000366 printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000367 (reg8&1)?"rw":"ro");
368
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000369 printk(BIOS_DEBUG, "Writing:\n");
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000370 *(volatile u8 *)0xfff00000 = 0x00;
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000371 printk(BIOS_DEBUG, "Testing:\n");
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000372 reg8 |= (1 << 0); /* set BIOSWE */
373 pci_write_config8(dev, 0xdc, reg8);
374
375 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000376 printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000377 (reg8&1)?"rw":"ro");
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000378 printk(BIOS_DEBUG, "Done.\n");
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000379#endif
380}
Stefan Reinauer269563a2009-01-19 21:20:22 +0000381#endif
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000382
Stefan Reinauera8e11682009-03-11 14:54:18 +0000383#define SPIBASE 0x3020
384static void i82801gx_spi_init(void)
385{
386 u16 spicontrol;
387
388 spicontrol = RCBA16(SPIBASE + 2);
389 spicontrol &= ~(1 << 0); // SPI Access Request
390 RCBA16(SPIBASE + 2) = spicontrol;
391}
392
Stefan Reinauer7a3d0952010-01-17 13:49:07 +0000393static void i82801gx_fixups(struct device *dev)
Stefan Reinauera8e11682009-03-11 14:54:18 +0000394{
395 /* This needs to happen after PCI enumeration */
396 RCBA32(0x1d40) |= 1;
Stefan Reinauer7a3d0952010-01-17 13:49:07 +0000397
398 /* USB Transient Disconnect Detect:
399 * Prevent a SE0 condition on the USB ports from being
400 * interpreted by the UHCI controller as a disconnect
401 */
402 pci_write_config8(dev, 0xad, 0x3);
Stefan Reinauera8e11682009-03-11 14:54:18 +0000403}
404
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000405static void lpc_init(struct device *dev)
406{
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000407 printk(BIOS_DEBUG, "i82801gx: lpc_init\n");
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000408
409 /* Set the value for PCI command register. */
410 pci_write_config16(dev, PCI_COMMAND, 0x000f);
411
412 /* IO APIC initialization. */
Paul Menzelddddf152013-04-23 14:40:23 +0200413 i82801gx_enable_ioapic(dev);
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000414
415 i82801gx_enable_serial_irqs(dev);
416
417 /* Setup the PIRQ. */
418 i82801gx_pirq_init(dev);
419
420 /* Setup power options. */
421 i82801gx_power_options(dev);
422
Stefan Reinauera8e11682009-03-11 14:54:18 +0000423 /* Configure Cx state registers */
424 i82801gx_configure_cstates(dev);
425
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000426 /* Set the state of the GPIO lines. */
427 //gpio_init(dev);
428
429 /* Initialize the real time clock. */
430 i82801gx_rtc_init(dev);
431
432 /* Initialize ISA DMA. */
433 isa_dma_init();
434
435 /* Initialize the High Precision Event Timers, if present. */
Stefan Reinauera8e11682009-03-11 14:54:18 +0000436 enable_hpet();
437
438 /* Initialize Clock Gating */
439 enable_clock_gating();
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000440
441 setup_i8259();
442
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000443 /* The OS should do this? */
Stefan Reinauer7a3d0952010-01-17 13:49:07 +0000444 /* Interrupt 9 should be level triggered (SCI) */
445 i8259_configure_irq_trigger(9, 1);
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000446
Stefan Reinauer08670622009-06-30 15:17:49 +0000447#if CONFIG_HAVE_SMI_HANDLER
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000448 i82801gx_lock_smm(dev);
Stefan Reinauer269563a2009-01-19 21:20:22 +0000449#endif
Stefan Reinauera8e11682009-03-11 14:54:18 +0000450
451 i82801gx_spi_init();
452
Stefan Reinauer7a3d0952010-01-17 13:49:07 +0000453 i82801gx_fixups(dev);
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000454}
455
Vladimir Serbinenkod5d94ea2014-10-18 02:13:11 +0200456unsigned long acpi_fill_madt(unsigned long current)
457{
458 /* Local APICs */
459 current = acpi_create_madt_lapics(current);
460
461 /* IOAPIC */
462 current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
463 2, IO_APIC_ADDR, 0);
464
465 /* LAPIC_NMI */
466 current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
467 current, 0,
468 MP_IRQ_POLARITY_HIGH |
469 MP_IRQ_TRIGGER_EDGE, 0x01);
470 current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
471 current, 1, MP_IRQ_POLARITY_HIGH |
472 MP_IRQ_TRIGGER_EDGE, 0x01);
473
474 /* INT_SRC_OVR */
475 current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
476 current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE);
477 current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
478 current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
479
480
481 return current;
482}
483
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +0200484void acpi_fill_fadt(acpi_fadt_t * fadt)
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200485{
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +0200486 device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
487 config_t *chip = dev->chip_info;
488 u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200489
490 fadt->pm1a_evt_blk = pmbase;
491 fadt->pm1b_evt_blk = 0x0;
492 fadt->pm1a_cnt_blk = pmbase + 0x4;
493 fadt->pm1b_cnt_blk = 0x0;
494 fadt->pm2_cnt_blk = pmbase + 0x20;
495 fadt->pm_tmr_blk = pmbase + 0x8;
496 fadt->gpe0_blk = pmbase + 0x28;
497 fadt->gpe1_blk = 0;
498
499 fadt->pm1_evt_len = 4;
500 fadt->pm1_cnt_len = 2;
501 fadt->pm2_cnt_len = 1;
502 fadt->pm_tmr_len = 4;
503 fadt->gpe0_blk_len = 8;
504 fadt->gpe1_blk_len = 0;
505 fadt->gpe1_base = 0;
506
507 fadt->reset_reg.space_id = 1;
508 fadt->reset_reg.bit_width = 8;
509 fadt->reset_reg.bit_offset = 0;
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +0200510 fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200511 fadt->reset_reg.addrl = 0xcf9;
512 fadt->reset_reg.addrh = 0;
513
514 fadt->reset_value = 6;
515
516 fadt->x_pm1a_evt_blk.space_id = 1;
517 fadt->x_pm1a_evt_blk.bit_width = 32;
518 fadt->x_pm1a_evt_blk.bit_offset = 0;
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +0200519 fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200520 fadt->x_pm1a_evt_blk.addrl = pmbase;
521 fadt->x_pm1a_evt_blk.addrh = 0x0;
522
523 fadt->x_pm1b_evt_blk.space_id = 0;
524 fadt->x_pm1b_evt_blk.bit_width = 0;
525 fadt->x_pm1b_evt_blk.bit_offset = 0;
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +0200526 fadt->x_pm1b_evt_blk.access_size = 0;
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200527 fadt->x_pm1b_evt_blk.addrl = 0x0;
528 fadt->x_pm1b_evt_blk.addrh = 0x0;
529
530 fadt->x_pm1a_cnt_blk.space_id = 1;
531 fadt->x_pm1a_cnt_blk.bit_width = 16;
532 fadt->x_pm1a_cnt_blk.bit_offset = 0;
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +0200533 fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200534 fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
535 fadt->x_pm1a_cnt_blk.addrh = 0x0;
536
537 fadt->x_pm1b_cnt_blk.space_id = 0;
538 fadt->x_pm1b_cnt_blk.bit_width = 0;
539 fadt->x_pm1b_cnt_blk.bit_offset = 0;
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +0200540 fadt->x_pm1b_cnt_blk.access_size = 0;
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200541 fadt->x_pm1b_cnt_blk.addrl = 0x0;
542 fadt->x_pm1b_cnt_blk.addrh = 0x0;
543
544 fadt->x_pm2_cnt_blk.space_id = 1;
545 fadt->x_pm2_cnt_blk.bit_width = 8;
546 fadt->x_pm2_cnt_blk.bit_offset = 0;
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +0200547 fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200548 fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
549 fadt->x_pm2_cnt_blk.addrh = 0x0;
550
551 fadt->x_pm_tmr_blk.space_id = 1;
552 fadt->x_pm_tmr_blk.bit_width = 32;
553 fadt->x_pm_tmr_blk.bit_offset = 0;
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +0200554 fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200555 fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
556 fadt->x_pm_tmr_blk.addrh = 0x0;
557
558 fadt->x_gpe0_blk.space_id = 1;
559 fadt->x_gpe0_blk.bit_width = 64;
560 fadt->x_gpe0_blk.bit_offset = 0;
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +0200561 fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200562 fadt->x_gpe0_blk.addrl = pmbase + 0x28;
563 fadt->x_gpe0_blk.addrh = 0x0;
564
565 fadt->x_gpe1_blk.space_id = 0;
566 fadt->x_gpe1_blk.bit_width = 0;
567 fadt->x_gpe1_blk.bit_offset = 0;
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +0200568 fadt->x_gpe1_blk.access_size = 0;
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200569 fadt->x_gpe1_blk.addrl = 0x0;
570 fadt->x_gpe1_blk.addrh = 0x0;
571 fadt->day_alrm = 0xd;
572 fadt->mon_alrm = 0x00;
573 fadt->century = 0x32;
574
575 fadt->model = 1;
576 fadt->sci_int = 0x9;
577 fadt->smi_cmd = APM_CNT;
578 fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
579 fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
580 fadt->s4bios_req = 0x0;
581 fadt->pstate_cnt = APM_CNT_PST_CONTROL;
582
583 fadt->cst_cnt = APM_CNT_CST_CONTROL;
584 fadt->p_lvl2_lat = 1;
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +0200585 fadt->p_lvl3_lat = chip->c3_latency;
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200586 fadt->flush_size = 0;
587 fadt->flush_stride = 0;
588 fadt->duty_offset = 1;
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +0200589 if (chip->p_cnt_throttling_supported) {
590 fadt->duty_width = 3;
591 } else {
592 fadt->duty_width = 0;
593 }
594 fadt->iapc_boot_arch = 0x03;
595 fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED
596 | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE
597 | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER
598 | ACPI_FADT_C2_MP_SUPPORTED);
599 if (chip->docking_supported) {
600 fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
601 }
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200602}
603
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000604static void i82801gx_lpc_read_resources(device_t dev)
605{
606 struct resource *res;
Vladimir Serbinenkof119f082014-11-24 21:05:56 +0100607 u8 io_index = 0;
608 int i;
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000609
610 /* Get the normal PCI resources of this device. */
611 pci_dev_read_resources(dev);
612
613 /* Add an extra subtractive resource for both memory and I/O. */
Vladimir Serbinenkof119f082014-11-24 21:05:56 +0100614 res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
Myles Watson29cc9ed2009-07-02 18:56:24 +0000615 res->base = 0;
616 res->size = 0x1000;
617 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
618 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000619
Vladimir Serbinenkof119f082014-11-24 21:05:56 +0100620 res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
Myles Watson29cc9ed2009-07-02 18:56:24 +0000621 res->base = 0xff800000;
622 res->size = 0x00800000; /* 8 MB for flash */
623 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
624 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
625
626 res = new_resource(dev, 3); /* IOAPIC */
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000627 res->base = IO_APIC_ADDR;
Myles Watson29cc9ed2009-07-02 18:56:24 +0000628 res->size = 0x00001000;
629 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
Vladimir Serbinenkof119f082014-11-24 21:05:56 +0100630
631 /* Set IO decode ranges if required.*/
632 for (i = 0; i < 4; i++) {
633 u32 gen_dec;
634 gen_dec = pci_read_config32(dev, 0x84 + 4 * i);
635
636 if ((gen_dec & 0xFFFC) > 0x1000) {
637 res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
638 res->base = gen_dec & 0xFFFC;
639 res->size = (gen_dec >> 16) & 0xFC;
640 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
641 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
642 }
643 }
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000644}
645
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000646static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
647{
Stefan Reinauera8e11682009-03-11 14:54:18 +0000648 if (!vendor || !device) {
649 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
650 pci_read_config32(dev, PCI_VENDOR_ID));
651 } else {
652 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
653 ((device & 0xffff) << 16) | (vendor & 0xffff));
654 }
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000655}
656
Alexander Couzensa90dad12015-04-12 21:49:46 +0200657static void southbridge_inject_dsdt(device_t dev)
Vladimir Serbinenko0e646172014-08-31 00:27:05 +0200658{
659 global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
660
661 if (gnvs) {
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +0100662 const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
663
Vladimir Serbinenko0e646172014-08-31 00:27:05 +0200664 memset(gnvs, 0, sizeof(*gnvs));
Vladimir Serbinenko385743a2014-10-18 02:26:21 +0200665
666 gnvs->apic = 1;
667 gnvs->mpen = 1; /* Enable Multi Processing */
668
Vladimir Serbinenko0e646172014-08-31 00:27:05 +0200669 acpi_create_gnvs(gnvs);
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +0100670
671 gnvs->ndid = gfx->ndid;
672 memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
673
Vladimir Serbinenko0e646172014-08-31 00:27:05 +0200674 /* And tell SMI about it */
675 smm_setup_structures(gnvs, NULL, NULL);
676
677 /* Add it to SSDT. */
Vladimir Serbinenko1bad88e2014-11-04 21:20:56 +0100678 acpigen_write_scope("\\");
679 acpigen_write_name_dword("NVSA", (u32) gnvs);
680 acpigen_pop_len();
Vladimir Serbinenko0e646172014-08-31 00:27:05 +0200681 }
682}
683
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000684static struct pci_operations pci_ops = {
685 .set_subsystem = set_subsystem,
686};
687
688static struct device_operations device_ops = {
689 .read_resources = i82801gx_lpc_read_resources,
690 .set_resources = pci_dev_set_resources,
Myles Watson7eac4452010-06-17 16:16:56 +0000691 .enable_resources = pci_dev_enable_resources,
Vladimir Serbinenko0e646172014-08-31 00:27:05 +0200692 .acpi_inject_dsdt_generator = southbridge_inject_dsdt,
693 .write_acpi_tables = acpi_write_hpet,
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000694 .init = lpc_init,
Kyösti Mälkkid0e212c2015-02-26 20:47:47 +0200695 .scan_bus = scan_lpc_bus,
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000696 .enable = i82801gx_enable,
697 .ops_pci = &pci_ops,
698};
699
Damien Zammitef33e032015-11-14 01:03:39 +1100700/* 27b0: 82801GH (ICH7 DH) */
701/* 27b8: 82801GB/GR (ICH7/ICH7R) */
702/* 27b9: 82801GBM/GU (ICH7-M/ICH7-U) */
703/* 27bc: 82NM10 (NM10) */
704/* 27bd: 82801GHM (ICH7-M DH) */
705
706static const unsigned short pci_device_ids[] = {
707 0x27b0, 0x27b8, 0x27b9, 0x27bc, 0x27bd, 0
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000708};
709
Damien Zammitef33e032015-11-14 01:03:39 +1100710static const struct pci_driver ich7_lpc __pci_driver = {
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000711 .ops = &device_ops,
712 .vendor = PCI_VENDOR_ID_INTEL,
Damien Zammitef33e032015-11-14 01:03:39 +1100713 .devices = pci_device_ids,
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000714};