Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
Timothy Pearson | 44e4a4e | 2015-08-11 17:49:06 -0500 | [diff] [blame] | 5 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #ifndef __SR5650_H__ |
| 18 | #define __SR5650_H__ |
| 19 | |
| 20 | #include <stdint.h> |
Timothy Pearson | 44e4a4e | 2015-08-11 17:49:06 -0500 | [diff] [blame] | 21 | #include <arch/acpi.h> |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 22 | #include <device/pci_ids.h> |
| 23 | #include "chip.h" |
| 24 | #include "rev.h" |
| 25 | |
| 26 | typedef struct __PCIE_CFG__ { |
| 27 | u16 Config; |
| 28 | u8 ResetReleaseDelay; |
| 29 | u8 Gfx0Width; |
| 30 | u8 Gfx1Width; |
| 31 | u8 GfxPayload; |
| 32 | u8 GppPayload; |
| 33 | u16 PortDetect; |
| 34 | u8 PortHp; /* hot plug */ |
| 35 | u16 DbgConfig; |
| 36 | u32 DbgConfig2; |
| 37 | u8 GfxLx; |
| 38 | u8 GppLx; |
| 39 | u8 NBSBLx; |
| 40 | u8 PortSlotInit; |
| 41 | u8 Gfx0Pwr; |
| 42 | u8 Gfx1Pwr; |
| 43 | u8 GppPwr; |
| 44 | } PCIE_CFG; |
| 45 | |
| 46 | /* PCIE config flags */ |
| 47 | #define PCIE_DUALSLOT_CONFIG (1 << 0) |
| 48 | #define PCIE_OVERCLOCK_ENABLE (1 << 1) |
| 49 | #define PCIE_GPP_CLK_GATING (1 << 2) |
| 50 | #define PCIE_ENABLE_STATIC_DEV_REMAP (1 << 3) |
| 51 | #define PCIE_OFF_UNUSED_GFX_LANES (1 << 4) |
| 52 | #define PCIE_OFF_UNUSED_GPP_LANES (1 << 5) |
| 53 | #define PCIE_DISABLE_HIDE_UNUSED_PORTS (1 << 7) |
| 54 | #define PCIE_GFX_CLK_GATING (1 << 11) |
| 55 | #define PCIE_GFX_COMPLIANCE (1 << 14) |
| 56 | #define PCIE_GPP_COMPLIANCE (1 << 15) |
| 57 | |
| 58 | /* -------------------- ---------------------- |
| 59 | * NBMISCIND |
| 60 | ------------------- -----------------------*/ |
| 61 | #define PCIE_LINK_CFG 0x8 |
| 62 | #define PCIE_NBCFG_REG7 0x37 |
| 63 | #define STRAPS_OUTPUT_MUX_7 0x67 |
| 64 | #define STRAPS_OUTPUT_MUX_A 0x6a |
| 65 | |
| 66 | /* -------------------- ---------------------- |
| 67 | * PCIEIND |
| 68 | ------------------- -----------------------*/ |
| 69 | #define PCIE_CI_CNTL 0x20 |
| 70 | #define PCIE_LC_LINK_WIDTH 0xa2 |
| 71 | #define PCIE_LC_STATE0 0xa5 |
| 72 | #define PCIE_VC0_RESOURCE_STATUS 0x12a /* 16bit read only */ |
| 73 | |
| 74 | #define PCIE_CORE_INDEX_SB (0x05 << 16) /* see rpr 4.3.2.2, bdg 2.1 */ |
| 75 | #define PCIE_CORE_INDEX_GPP1 (0x04 << 16) |
| 76 | #define PCIE_CORE_INDEX_GPP2 (0x06 << 16) |
| 77 | #define PCIE_CORE_INDEX_GPP1_GPP2 (0x00 << 16) |
| 78 | #define PCIE_CORE_INDEX_GPP3a (0x07 << 16) |
| 79 | #define PCIE_CORE_INDEX_GPP3b (0x03 << 16) |
| 80 | |
| 81 | /* contents of PCIE_VC0_RESOURCE_STATUS */ |
| 82 | #define VC_NEGOTIATION_PENDING (1 << 1) |
| 83 | |
| 84 | #define LC_STATE_RECONFIG_GPPSB 0x10 |
| 85 | |
| 86 | /* ------------------------------------------------ |
| 87 | * Global variable |
| 88 | * ------------------------------------------------- */ |
| 89 | extern PCIE_CFG AtiPcieCfg; |
| 90 | |
Martin Roth | 55e31a9 | 2014-12-16 20:53:49 -0700 | [diff] [blame] | 91 | /* ----------------- export functions ----------------- */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 92 | u32 nbpcie_p_read_index(device_t dev, u32 index); |
| 93 | void nbpcie_p_write_index(device_t dev, u32 index, u32 data); |
| 94 | u32 nbpcie_ind_read_index(device_t nb_dev, u32 index); |
| 95 | void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data); |
Timothy Pearson | 44e4a4e | 2015-08-11 17:49:06 -0500 | [diff] [blame] | 96 | uint32_t l2cfg_ind_read_index(device_t nb_dev, uint32_t index); |
| 97 | void l2cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data); |
| 98 | uint32_t l1cfg_ind_read_index(device_t nb_dev, uint32_t index); |
| 99 | void l1cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 100 | u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg); |
| 101 | void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val); |
| 102 | void sr5650_set_tom(device_t nb_dev); |
| 103 | |
Timothy Pearson | 44e4a4e | 2015-08-11 17:49:06 -0500 | [diff] [blame] | 104 | unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, |
| 105 | struct acpi_rsdp *rsdp); |
| 106 | |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 107 | void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add); |
| 108 | void enable_pcie_bar3(device_t nb_dev); |
| 109 | void disable_pcie_bar3(device_t nb_dev); |
| 110 | |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 111 | void enable_sr5650_dev8(void); |
| 112 | void sr5650_htinit(void); |
Timothy Pearson | 44e4a4e | 2015-08-11 17:49:06 -0500 | [diff] [blame] | 113 | void sr5650_htinit_dect_and_enable_isochronous_link(void); |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 114 | void sr5650_early_setup(void); |
| 115 | void sr5650_before_pci_init(void); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 116 | void sr5650_enable(device_t dev); |
| 117 | void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port); |
| 118 | void sr5650_gfx_init(device_t nb_dev, device_t dev, u32 port); |
| 119 | void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev); |
| 120 | void config_gpp_core(device_t nb_dev, device_t sb_dev); |
| 121 | void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port); |
| 122 | u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port); |
| 123 | void pcie_config_misc_clk(device_t nb_dev); |
| 124 | void fam10_optimization(void); |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 125 | void sr5650_disable_pcie_bridge(void); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 126 | u32 get_vid_did(device_t dev); |
Timothy Pearson | 44e4a4e | 2015-08-11 17:49:06 -0500 | [diff] [blame] | 127 | void detect_and_enable_iommu(device_t iommu_dev); |
| 128 | void sr5650_iommu_read_resources(device_t dev); |
| 129 | void sr5650_iommu_set_resources(device_t dev); |
| 130 | void sr5650_iommu_enable_resources(device_t dev); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 131 | void sr5650_nb_pci_table(device_t nb_dev); |
| 132 | void init_gen2(device_t nb_dev, device_t dev, u8 port); |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 133 | void sr56x0_lock_hwinitreg(void); |
Timothy Pearson | 1eaaa0e | 2015-08-14 15:20:42 -0500 | [diff] [blame] | 134 | struct resource * sr5650_retrieve_cpu_mmio_resource(void); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 135 | #endif /* SR5650_H */ |