Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
Timothy Pearson | 4731423 | 2015-10-23 22:16:55 -0500 | [diff] [blame] | 5 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pci_ids.h> |
| 21 | #include <device/pci_ops.h> |
| 22 | #include <device/smbus.h> |
| 23 | #include <pc80/mc146818rtc.h> |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 24 | #include <arch/io.h> |
| 25 | #include <cpu/x86/lapic.h> |
| 26 | #include <arch/ioapic.h> |
| 27 | #include <stdlib.h> |
| 28 | #include "sb700.h" |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 29 | #include "smbus.h" |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 30 | |
| 31 | #define NMI_OFF 0 |
| 32 | |
Timothy Pearson | 0a105cd | 2015-12-08 12:09:06 -0600 | [diff] [blame] | 33 | #define SB_MMIO_CFG_REG 0x9c |
| 34 | #define SB_MMIO_BASE_ADDRESS 0xfeb00000 |
| 35 | |
Timothy Pearson | acbdade | 2015-10-17 04:36:47 -0500 | [diff] [blame] | 36 | #define PRIMARY_SMBUS_RESOURCE_NUMBER 0x90 |
| 37 | #define AUXILIARY_SMBUS_RESOURCE_NUMBER 0x58 |
| 38 | |
| 39 | uint8_t amd_sb700_aux_smbus = 0; |
| 40 | |
Timothy Pearson | 4731423 | 2015-10-23 22:16:55 -0500 | [diff] [blame] | 41 | enum power_mode { |
| 42 | POWER_MODE_OFF = 0, |
| 43 | POWER_MODE_ON = 1, |
| 44 | POWER_MODE_LAST = 2, |
| 45 | }; |
| 46 | |
| 47 | #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL |
| 48 | #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL POWER_MODE_ON |
| 49 | #endif |
| 50 | |
| 51 | static const char* power_mode_names[] = { |
| 52 | [POWER_MODE_OFF] = "off", |
| 53 | [POWER_MODE_ON] = "on", |
| 54 | [POWER_MODE_LAST] = "last", |
| 55 | }; |
| 56 | |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 57 | /* |
| 58 | * SB700 enables all USB controllers by default in SMBUS Control. |
| 59 | * SB700 enables SATA by default in SMBUS Control. |
| 60 | */ |
| 61 | static void sm_init(device_t dev) |
| 62 | { |
| 63 | u8 byte; |
| 64 | u8 byte_old; |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 65 | u8 rev; |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 66 | u32 dword; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 67 | void *ioapic_base; |
Timothy Pearson | 4731423 | 2015-10-23 22:16:55 -0500 | [diff] [blame] | 68 | uint32_t power_state; |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 69 | u32 nmi_option; |
| 70 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 71 | printk(BIOS_INFO, "sm_init().\n"); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 72 | |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 73 | rev = get_sb700_revision(dev); |
Timothy Pearson | ee3ec8e | 2015-10-23 22:28:26 -0500 | [diff] [blame] | 74 | /* This works in a similar fashion to a memory resource, but without an enable bit */ |
| 75 | ioapic_base = (void *)(pci_read_config32(dev, 0x74) & (0xffffffe0)); |
| 76 | setup_ioapic(ioapic_base, 0); /* Don't rename IOAPIC ID. */ |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 77 | |
| 78 | /* 2.10 Interrupt Routing/Filtering */ |
| 79 | dword = pci_read_config8(dev, 0x62); |
| 80 | dword |= 3; |
| 81 | pci_write_config8(dev, 0x62, dword); |
| 82 | |
| 83 | /* Delay back to back interrupts to the CPU. */ |
| 84 | dword = pci_read_config16(dev, 0x64); |
| 85 | dword |= 1 << 13; |
| 86 | pci_write_config16(dev, 0x64, dword); |
| 87 | |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 88 | /* rrg:K8 INTR Enable (BIOS should set this bit after PIC initialization) */ |
| 89 | /* rpr 2.1 Enabling Legacy Interrupt */ |
| 90 | dword = pci_read_config8(dev, 0x62); |
| 91 | dword |= 1 << 2; |
| 92 | pci_write_config8(dev, 0x62, dword); |
| 93 | |
| 94 | dword = pci_read_config32(dev, 0x78); |
| 95 | dword |= 1 << 9; |
| 96 | pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */ |
| 97 | |
| 98 | /* bit 10: MultiMediaTimerIrqEn */ |
| 99 | dword = pci_read_config8(dev, 0x64); |
| 100 | dword |= 1 << 10; |
| 101 | pci_write_config8(dev, 0x64, dword); |
| 102 | /* enable serial irq */ |
| 103 | byte = pci_read_config8(dev, 0x69); |
| 104 | byte |= 1 << 7; /* enable serial irq function */ |
| 105 | byte &= ~(0xF << 2); |
| 106 | byte |= 4 << 2; /* set NumSerIrqBits=4 */ |
| 107 | pci_write_config8(dev, 0x69, byte); |
| 108 | |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 109 | /* Sx State Settings |
| 110 | * Note: These 2 registers need to be set correctly for the S-state |
| 111 | * to work properly. Otherwise the system may hang during resume |
| 112 | * from the S-state. |
| 113 | */ |
| 114 | /*Use 8us clock for delays in the S-state resume timing sequence.*/ |
| 115 | byte = pm_ioread(0x65); |
| 116 | byte &= ~(1 << 7); |
| 117 | pm_iowrite(0x65, byte); |
| 118 | /* Delay the APIC interrupt to the CPU until the system has fully resumed from the S-state. */ |
| 119 | byte = pm_ioread(0x68); |
| 120 | byte |= 1 << 2; |
| 121 | pm_iowrite(0x68, byte); |
| 122 | |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 123 | /* IRQ0From8254 */ |
| 124 | byte = pci_read_config8(dev, 0x41); |
| 125 | byte &= ~(1 << 7); |
| 126 | pci_write_config8(dev, 0x41, byte); |
| 127 | |
| 128 | byte = pm_ioread(0x61); |
Timothy Pearson | 83abd81 | 2015-06-08 19:35:06 -0500 | [diff] [blame] | 129 | if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) |
| 130 | byte &= ~(1 << 1); /* Clear for non-K8 CPUs */ |
| 131 | else |
| 132 | byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */ |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 133 | pm_iowrite(0x61, byte); |
| 134 | |
| 135 | /* disable SMI */ |
| 136 | byte = pm_ioread(0x53); |
| 137 | byte |= 1 << 3; |
| 138 | pm_iowrite(0x53, byte); |
| 139 | |
| 140 | /* power after power fail */ |
Timothy Pearson | 4731423 | 2015-10-23 22:16:55 -0500 | [diff] [blame] | 141 | power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; |
| 142 | get_option(&power_state, "power_on_after_fail"); |
| 143 | if (power_state > 2) { |
| 144 | printk(BIOS_WARNING, "Invalid power_on_after_fail setting, using default\n"); |
| 145 | power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; |
| 146 | } |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 147 | byte = pm_ioread(0x74); |
| 148 | byte &= ~0x03; |
Timothy Pearson | 4731423 | 2015-10-23 22:16:55 -0500 | [diff] [blame] | 149 | if (power_state == POWER_MODE_OFF) |
| 150 | byte |= 0x0; |
| 151 | else if (power_state == POWER_MODE_ON) |
| 152 | byte |= 0x1; |
| 153 | else if (power_state == POWER_MODE_LAST) |
| 154 | byte |= 0x2; |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 155 | byte |= 1 << 2; |
| 156 | pm_iowrite(0x74, byte); |
Timothy Pearson | 4731423 | 2015-10-23 22:16:55 -0500 | [diff] [blame] | 157 | printk(BIOS_INFO, "set power \"%s\" after power fail\n", power_mode_names[power_state]); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 158 | |
| 159 | byte = pm_ioread(0x68); |
| 160 | byte &= ~(1 << 1); |
| 161 | /* 2.7 */ |
| 162 | byte |= 1 << 2; |
| 163 | pm_iowrite(0x68, byte); |
| 164 | |
| 165 | /* 2.7 */ |
| 166 | byte = pm_ioread(0x65); |
| 167 | byte &= ~(1 << 7); |
| 168 | pm_iowrite(0x65, byte); |
| 169 | |
| 170 | /* 2.16 */ |
| 171 | byte = pm_ioread(0x55); |
| 172 | byte |= 1 << 5; |
| 173 | pm_iowrite(0x55, byte); |
| 174 | |
| 175 | byte = pm_ioread(0xD7); |
Idwer Vollering | d26da9c | 2013-12-22 21:38:18 +0000 | [diff] [blame] | 176 | byte |= 1 << 6 | 1 << 1; |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 177 | pm_iowrite(0xD7, byte); |
| 178 | |
| 179 | /* 2.15 */ |
| 180 | byte = pm_ioread(0x42); |
| 181 | byte &= ~(1 << 2); |
| 182 | pm_iowrite(0x42, byte); |
| 183 | |
| 184 | /* Set up NMI on errors */ |
| 185 | byte = inb(0x70); /* RTC70 */ |
| 186 | byte_old = byte; |
| 187 | nmi_option = NMI_OFF; |
| 188 | get_option(&nmi_option, "nmi"); |
| 189 | if (nmi_option) { |
| 190 | byte &= ~(1 << 7); /* set NMI */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 191 | printk(BIOS_INFO, "++++++++++set NMI+++++\n"); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 192 | } else { |
| 193 | byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 194 | printk(BIOS_INFO, "++++++++++no set NMI+++++\n"); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 195 | } |
| 196 | byte &= ~(1 << 7); |
| 197 | if (byte != byte_old) { |
| 198 | outb(byte, 0x70); |
| 199 | } |
| 200 | |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 201 | /*rpr v2.13 2.22 SMBUS PCI Config */ |
| 202 | byte = pci_read_config8(dev, 0xE1); |
| 203 | if ((REV_SB700_A11 == rev) || REV_SB700_A12 == rev) { |
| 204 | byte |= 1 << 0; |
| 205 | } |
Martin Roth | dcf253c | 2014-12-16 20:51:31 -0700 | [diff] [blame] | 206 | /*Set bit2 to 1, enable Io port 60h read/write SMi trapping and |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 207 | *Io port 64h write Smi trapping. conflict with ps2 keyboard |
| 208 | */ |
| 209 | //byte |= 1 << 2 | 1 << 3 | 1 << 4; |
| 210 | byte |= 1 << 3 | 1 << 4; |
| 211 | pci_write_config8(dev, 0xE1, byte); |
| 212 | |
| 213 | /* 2.5 Enabling Non-Posted Memory Write */ |
| 214 | axindxc_reg(0x10, 1 << 9, 1 << 9); |
| 215 | |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 216 | /* 2.11 IO Trap Settings */ |
| 217 | abcfg_reg(0x10090, 1 << 16, 1 << 16); |
| 218 | |
| 219 | /* ab index */ |
| 220 | pci_write_config32(dev, 0xF0, AB_INDX); |
| 221 | /* Initialize the real time clock */ |
Gabe Black | b3f08c6 | 2014-04-30 17:12:25 -0700 | [diff] [blame] | 222 | cmos_init(0); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 223 | |
| 224 | /* 4.3 Enabling Upstream DMA Access */ |
| 225 | axcfg_reg(0x04, 1 << 2, 1 << 2); |
| 226 | /* 4.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */ |
| 227 | abcfg_reg(0x10060, 9 << 17, 9 << 17); |
| 228 | abcfg_reg(0x10064, 9 << 17, 9 << 17); |
| 229 | |
| 230 | /* 4.5 Enabling OHCI Prefetch for Performance Enhancement, A12 */ |
| 231 | abcfg_reg(0x80, 1 << 0, 1<< 0); |
| 232 | |
| 233 | /* 4.6 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */ |
| 234 | /* 4.7 Enabling Additional Address Bits Checking in Downstream */ |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 235 | /* 4.16 IO write and SMI ordering enhancement*/ |
| 236 | abcfg_reg(0x9c, 3 << 0, 3 << 0); |
| 237 | if (REV_SB700_A12 == rev) { |
| 238 | abcfg_reg(0x9c, 1 << 8, 1 << 8); |
| 239 | } else if (rev >= REV_SB700_A14) { |
| 240 | abcfg_reg(0x9c, 1 << 8, 0 << 8); |
| 241 | } |
| 242 | if (REV_SB700_A15 == rev) { |
| 243 | abcfg_reg(0x90, 1 << 21, 1 << 21); |
| 244 | abcfg_reg(0x9c, 1 << 5 | 1 << 9 | 1 << 15, 1 << 5 | 1 << 9 | 1 << 15); |
| 245 | } |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 246 | |
| 247 | /* 4.8 Set B-Link Prefetch Mode */ |
| 248 | abcfg_reg(0x80, 3 << 17, 3 << 17); |
| 249 | |
| 250 | /* 4.9 Enabling Detection of Upstream Interrupts */ |
| 251 | abcfg_reg(0x94, 1 << 20 | 0x7FFFF, 1 << 20 | 0x00FEE); |
| 252 | |
| 253 | /* 4.10: Enabling Downstream Posted Transactions to Pass Non-Posted |
| 254 | * Transactions for the K8 Platform (for All Revisions) */ |
| 255 | abcfg_reg(0x10090, 1 << 8, 1 << 8); |
| 256 | |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 257 | /* Set ACPI Software clock Throttling Period to 244 us*/ |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 258 | byte = pm_ioread(0x68); |
| 259 | byte &= ~(3 << 6); |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 260 | byte |= (2 << 6); /* 244us */ |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 261 | pm_iowrite(0x68, byte); |
| 262 | |
| 263 | if (REV_SB700_A15 == rev) { |
| 264 | u16 word; |
| 265 | |
| 266 | /* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */ |
| 267 | axindxc_reg(0x02, 1 << 9, 1 << 9); |
| 268 | abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0); |
| 269 | abcfg_reg(0x1009C, 0x00000030, 0x00000030); |
| 270 | abcfg_reg(0x10090, 0x00001E00, 0x00001E00); |
| 271 | |
| 272 | /* rpr v2.13 4.19 Enabling Posted Pass Non-Posted Upstream */ |
| 273 | abcfg_reg(0x58, 0x0000F800, 0x0000E800); |
| 274 | |
| 275 | /* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */ |
| 276 | axindxc_reg(0x02, 1 << 10, 1 << 10); |
| 277 | |
| 278 | /* rpr v2.13 2.38 Unconditional Shutdown */ |
| 279 | byte = pci_read_config8(dev, 0x43); |
| 280 | byte &= ~(1 << 3); |
| 281 | pci_write_config8(dev, 0x43, byte); |
| 282 | |
| 283 | word = pci_read_config16(dev, 0x38); |
| 284 | word |= 1 << 12; |
| 285 | pci_write_config16(dev, 0x38, word); |
| 286 | |
| 287 | byte |= 1 << 3; |
| 288 | pci_write_config8(dev, 0x43, byte); |
Timothy Pearson | 0a105cd | 2015-12-08 12:09:06 -0600 | [diff] [blame] | 289 | |
| 290 | /* Enable southbridge MMIO decode */ |
| 291 | dword = pci_read_config32(dev, SB_MMIO_CFG_REG); |
| 292 | dword &= ~(0xffffff << 8); |
| 293 | dword |= SB_MMIO_BASE_ADDRESS; |
| 294 | dword |= 0x1; |
| 295 | pci_write_config32(dev, SB_MMIO_CFG_REG, dword); |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 296 | } |
| 297 | //ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER |
| 298 | byte = pci_read_config8(dev, 0xAE); |
| 299 | byte |= 1 << 5; |
| 300 | pci_write_config8(dev, 0xAE, byte); |
| 301 | |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 302 | /* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */ |
| 303 | /* 4.12: Enabling AB and BIF Clock Gating */ |
| 304 | abcfg_reg(0x10054, 0xFFFF0000, 0x1040000); |
| 305 | abcfg_reg(0x54, 0xFF << 16, 4 << 16); |
| 306 | abcfg_reg(0x54, 1 << 24, 0 << 24); |
| 307 | abcfg_reg(0x98, 0x0000FF00, 0x00004700); |
| 308 | |
| 309 | /* 4.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */ |
| 310 | abcfg_reg(0x10054, 0x0000FFFF, 0x07FF); |
| 311 | |
| 312 | /* 4.14:Enabling Requester ID for upstream traffic. */ |
| 313 | abcfg_reg(0x98, 1 << 16, 1 << 16); |
| 314 | |
Zheng Bao | 2a5101a | 2010-10-10 15:18:53 +0000 | [diff] [blame] | 315 | /* 9.2: Enabling IDE Data Bus DD7 Pull Down Resistor */ |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 316 | byte = pm2_ioread(0xE5); |
| 317 | byte |= 1 << 2; |
| 318 | pm2_iowrite(0xE5, byte); |
| 319 | |
| 320 | /* Enable IDE controller. */ |
| 321 | byte = pm_ioread(0x59); |
| 322 | byte &= ~(1 << 1); |
| 323 | pm_iowrite(0x59, byte); |
| 324 | |
Timothy Pearson | ee3ec8e | 2015-10-23 22:28:26 -0500 | [diff] [blame] | 325 | /* Enable SCI as irq9. */ |
| 326 | outb(0x4, 0xC00); |
| 327 | outb(0x9, 0xC01); |
| 328 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 329 | printk(BIOS_INFO, "sm_init() end\n"); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 330 | |
| 331 | /* Enable NbSb virtual channel */ |
| 332 | axcfg_reg(0x114, 0x3f << 1, 0 << 1); |
| 333 | axcfg_reg(0x120, 0x7f << 1, 0x7f << 1); |
| 334 | axcfg_reg(0x120, 7 << 24, 1 << 24); |
| 335 | axcfg_reg(0x120, 1 << 31, 1 << 31); |
| 336 | abcfg_reg(0x50, 1 << 3, 1 << 3); |
| 337 | } |
| 338 | |
| 339 | static int lsmbus_recv_byte(device_t dev) |
| 340 | { |
| 341 | u32 device; |
| 342 | struct resource *res; |
| 343 | struct bus *pbus; |
| 344 | |
| 345 | device = dev->path.i2c.device; |
| 346 | pbus = get_pbus_smbus(dev); |
| 347 | |
Timothy Pearson | acbdade | 2015-10-17 04:36:47 -0500 | [diff] [blame] | 348 | if (!amd_sb700_aux_smbus) |
| 349 | res = find_resource(pbus->dev, PRIMARY_SMBUS_RESOURCE_NUMBER); |
| 350 | else |
| 351 | res = find_resource(pbus->dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 352 | |
| 353 | return do_smbus_recv_byte(res->base, device); |
| 354 | } |
| 355 | |
| 356 | static int lsmbus_send_byte(device_t dev, u8 val) |
| 357 | { |
| 358 | u32 device; |
| 359 | struct resource *res; |
| 360 | struct bus *pbus; |
| 361 | |
| 362 | device = dev->path.i2c.device; |
| 363 | pbus = get_pbus_smbus(dev); |
| 364 | |
Timothy Pearson | acbdade | 2015-10-17 04:36:47 -0500 | [diff] [blame] | 365 | if (!amd_sb700_aux_smbus) |
| 366 | res = find_resource(pbus->dev, PRIMARY_SMBUS_RESOURCE_NUMBER); |
| 367 | else |
| 368 | res = find_resource(pbus->dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 369 | |
| 370 | return do_smbus_send_byte(res->base, device, val); |
| 371 | } |
| 372 | |
| 373 | static int lsmbus_read_byte(device_t dev, u8 address) |
| 374 | { |
| 375 | u32 device; |
| 376 | struct resource *res; |
| 377 | struct bus *pbus; |
| 378 | |
| 379 | device = dev->path.i2c.device; |
| 380 | pbus = get_pbus_smbus(dev); |
| 381 | |
Timothy Pearson | acbdade | 2015-10-17 04:36:47 -0500 | [diff] [blame] | 382 | if (!amd_sb700_aux_smbus) |
| 383 | res = find_resource(pbus->dev, PRIMARY_SMBUS_RESOURCE_NUMBER); |
| 384 | else |
| 385 | res = find_resource(pbus->dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 386 | |
| 387 | return do_smbus_read_byte(res->base, device, address); |
| 388 | } |
| 389 | |
| 390 | static int lsmbus_write_byte(device_t dev, u8 address, u8 val) |
| 391 | { |
| 392 | u32 device; |
| 393 | struct resource *res; |
| 394 | struct bus *pbus; |
| 395 | |
| 396 | device = dev->path.i2c.device; |
| 397 | pbus = get_pbus_smbus(dev); |
| 398 | |
Timothy Pearson | acbdade | 2015-10-17 04:36:47 -0500 | [diff] [blame] | 399 | if (!amd_sb700_aux_smbus) |
| 400 | res = find_resource(pbus->dev, PRIMARY_SMBUS_RESOURCE_NUMBER); |
| 401 | else |
| 402 | res = find_resource(pbus->dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 403 | |
| 404 | return do_smbus_write_byte(res->base, device, address, val); |
| 405 | } |
Zheng Bao | bfca8ef | 2010-06-19 06:55:17 +0000 | [diff] [blame] | 406 | |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 407 | static struct smbus_bus_operations lops_smbus_bus = { |
| 408 | .recv_byte = lsmbus_recv_byte, |
| 409 | .send_byte = lsmbus_send_byte, |
| 410 | .read_byte = lsmbus_read_byte, |
| 411 | .write_byte = lsmbus_write_byte, |
| 412 | }; |
| 413 | |
| 414 | static void sb700_sm_read_resources(device_t dev) |
| 415 | { |
| 416 | struct resource *res; |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 417 | |
| 418 | /* Get the normal pci resources of this device */ |
Timothy Pearson | ee3ec8e | 2015-10-23 22:28:26 -0500 | [diff] [blame] | 419 | pci_dev_read_resources(dev); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 420 | |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 421 | /* apic */ |
| 422 | res = new_resource(dev, 0x74); |
Uwe Hermann | 74d1a6e | 2010-10-12 17:34:08 +0000 | [diff] [blame] | 423 | res->base = IO_APIC_ADDR; |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 424 | res->size = 256 * 0x10; |
| 425 | res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ |
| 426 | res->align = 8; |
| 427 | res->gran = 8; |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 428 | res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 429 | |
Timothy Pearson | 0a105cd | 2015-12-08 12:09:06 -0600 | [diff] [blame] | 430 | /* SB MMIO / WDT */ |
| 431 | res = new_resource(dev, SB_MMIO_CFG_REG); |
| 432 | res->base = SB_MMIO_BASE_ADDRESS; |
| 433 | res->size = 0x1000; |
| 434 | res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ |
| 435 | res->align = 8; |
| 436 | res->gran = 8; |
| 437 | res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; |
| 438 | |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 439 | /* HPET */ |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 440 | res = new_resource(dev, 0xB4); /* TODO: test hpet */ |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 441 | res->base = 0xfed00000; /* reset hpet to widely accepted address */ |
| 442 | res->size = 0x400; |
| 443 | res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ |
| 444 | res->align = 8; |
| 445 | res->gran = 8; |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 446 | res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 447 | |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 448 | /* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */ |
| 449 | |
Timothy Pearson | acbdade | 2015-10-17 04:36:47 -0500 | [diff] [blame] | 450 | /* primary smbus */ |
| 451 | res = new_resource(dev, PRIMARY_SMBUS_RESOURCE_NUMBER); |
| 452 | res->base = SMBUS_IO_BASE; |
| 453 | res->size = 0x10; |
| 454 | res->limit = 0xFFFFUL; /* res->base + res->size -1; */ |
| 455 | res->align = 8; |
| 456 | res->gran = 8; |
| 457 | res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; |
| 458 | |
| 459 | /* auxiliary smbus */ |
| 460 | res = new_resource(dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); |
| 461 | res->base = SMBUS_AUX_IO_BASE; |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 462 | res->size = 0x10; |
| 463 | res->limit = 0xFFFFUL; /* res->base + res->size -1; */ |
| 464 | res->align = 8; |
| 465 | res->gran = 8; |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 466 | res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 467 | |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 468 | compact_resources(dev); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 469 | } |
Zheng Bao | bfca8ef | 2010-06-19 06:55:17 +0000 | [diff] [blame] | 470 | |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 471 | static void sb700_sm_set_resources(struct device *dev) |
| 472 | { |
| 473 | struct resource *res; |
| 474 | u8 byte; |
| 475 | |
| 476 | pci_dev_set_resources(dev); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 477 | res = find_resource(dev, 0x74); |
| 478 | pci_write_config32(dev, 0x74, res->base | 1 << 3); |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 479 | |
| 480 | /* TODO: test hpet */ |
| 481 | #if 0 //rrg-2.0.3 shows BAR1 not used |
| 482 | /* Make SMBUS BAR1(HPET base at offset 14h) visible */ |
| 483 | byte = pci_read_config8(dev, 0x43); |
| 484 | byte &= ~(1 << 3); |
| 485 | pci_write_config8(dev, 0x43, byte); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 486 | #endif |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 487 | |
| 488 | res = find_resource(dev, 0xB4); |
| 489 | /* Program HPET BAR Address */ |
| 490 | pci_write_config32(dev, 0xB4, res->base); |
| 491 | |
| 492 | /* Enable decoding of HPET MMIO, enable HPET MSI */ |
| 493 | byte = pci_read_config8(dev, 0x43); |
| 494 | //byte |= (1 << 3); // Make SMBus Bar1 invisible |
| 495 | //byte |= ((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); |
| 496 | byte |= (1 << 4); |
| 497 | pci_write_config8(dev, 0x43, byte); |
| 498 | |
| 499 | /* Enable HPET irq */ |
| 500 | byte = pci_read_config8(dev, 0x65); |
| 501 | byte |= (1 << 2); |
| 502 | pci_write_config8(dev, 0x65, byte); |
| 503 | /* TODO: End of test hpet */ |
| 504 | |
Timothy Pearson | acbdade | 2015-10-17 04:36:47 -0500 | [diff] [blame] | 505 | res = find_resource(dev, PRIMARY_SMBUS_RESOURCE_NUMBER); |
| 506 | pci_write_config32(dev, PRIMARY_SMBUS_RESOURCE_NUMBER, res->base | 1); |
| 507 | |
| 508 | res = find_resource(dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); |
| 509 | pci_write_config32(dev, AUXILIARY_SMBUS_RESOURCE_NUMBER, res->base | 1); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 510 | } |
| 511 | |
| 512 | static struct pci_operations lops_pci = { |
| 513 | .set_subsystem = pci_dev_set_subsystem, |
| 514 | }; |
Zheng Bao | bfca8ef | 2010-06-19 06:55:17 +0000 | [diff] [blame] | 515 | |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 516 | static struct device_operations smbus_ops = { |
| 517 | .read_resources = sb700_sm_read_resources, |
| 518 | .set_resources = sb700_sm_set_resources, |
| 519 | .enable_resources = pci_dev_enable_resources, |
| 520 | .init = sm_init, |
Kyösti Mälkki | d0e212c | 2015-02-26 20:47:47 +0200 | [diff] [blame] | 521 | .scan_bus = scan_smbus, |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 522 | .ops_pci = &lops_pci, |
| 523 | .ops_smbus_bus = &lops_smbus_bus, |
| 524 | }; |
Zheng Bao | bfca8ef | 2010-06-19 06:55:17 +0000 | [diff] [blame] | 525 | |
Stefan Reinauer | 8e96ba2 | 2010-03-16 23:33:29 +0000 | [diff] [blame] | 526 | static const struct pci_driver smbus_driver __pci_driver = { |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 527 | .ops = &smbus_ops, |
| 528 | .vendor = PCI_VENDOR_ID_ATI, |
| 529 | .device = PCI_DEVICE_ID_ATI_SB700_SM, |
| 530 | }; |