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huang linbfdd7322014-09-25 16:33:38 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2014 Rockchip Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
huang linbfdd7322014-09-25 16:33:38 +080014 */
15
huang linbfdd7322014-09-25 16:33:38 +080016#include <arch/io.h>
huang linbfdd7322014-09-25 16:33:38 +080017#include <assert.h>
Julius Werner7a453eb2014-10-20 13:14:55 -070018#include <console/console.h>
huang linbfdd7322014-09-25 16:33:38 +080019#include <delay.h>
Julius Werner7a453eb2014-10-20 13:14:55 -070020#include <soc/addressmap.h>
21#include <soc/grf.h>
22#include <soc/soc.h>
23#include <soc/pwm.h>
24#include <soc/clock.h>
25#include <stdlib.h>
26#include <timer.h>
huang linbfdd7322014-09-25 16:33:38 +080027
28struct pwm_ctl {
29 u32 pwm_cnt;
30 u32 pwm_period_hpr;
31 u32 pwm_duty_lpr;
32 u32 pwm_ctrl;
33};
34
35struct rk3288_pwm_regs {
36 struct pwm_ctl pwm[4];
37 u32 intsts;
38 u32 int_en;
39};
40check_member(rk3288_pwm_regs, int_en, 0x44);
41
42#define RK_PWM_DISABLE (0 << 0)
43#define RK_PWM_ENABLE (1 << 0)
44
45
46#define PWM_ONE_SHOT (0 << 1)
47#define PWM_CONTINUOUS (1 << 1)
48#define RK_PWM_CAPTURE (1 << 2)
49
50#define PWM_DUTY_POSTIVE (1 << 3)
51#define PWM_DUTY_NEGATIVE (0 << 3)
52
53#define PWM_INACTIVE_POSTIVE (1 << 4)
54#define PWM_INACTIVE_NEGATIVE (0 << 4)
55
56#define PWM_OUTPUT_LEFT (0 << 5)
57#define PWM_OUTPUT_CENTER (1 << 5)
58
59#define PWM_LP_ENABLE (1 << 8)
60#define PWM_LP_DISABLE (0 << 8)
61
62#define PWM_SEL_SCALE_CLK (1 << 9)
63#define PWM_SEL_SRC_CLK (0 << 9)
64
65struct rk3288_pwm_regs *rk3288_pwm = (void *)RK_PWM0123_BASE;
66
67void pwm_init(u32 id, u32 period_ns, u32 duty_ns)
68{
69 unsigned long period, duty;
70
71 /*use rk pwm*/
Julius Werner2f37bd62015-02-19 14:51:15 -080072 write32(&rk3288_grf->soc_con2, RK_SETBITS(1 << 0));
huang linbfdd7322014-09-25 16:33:38 +080073
Julius Werner94184762015-02-19 20:19:23 -080074 write32(&rk3288_pwm->pwm[id].pwm_ctrl, PWM_SEL_SRC_CLK |
75 PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_CONTINUOUS |
76 PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE | RK_PWM_DISABLE);
huang linbfdd7322014-09-25 16:33:38 +080077
78 period = (PD_BUS_PCLK_HZ / 1000) * period_ns / USECS_PER_SEC;
79 duty = (PD_BUS_PCLK_HZ / 1000) * duty_ns / USECS_PER_SEC;
80
Julius Werner2f37bd62015-02-19 14:51:15 -080081 write32(&rk3288_pwm->pwm[id].pwm_period_hpr, period);
82 write32(&rk3288_pwm->pwm[id].pwm_duty_lpr, duty);
huang linbfdd7322014-09-25 16:33:38 +080083 setbits_le32(&rk3288_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE);
84}