Furquan Shaikh | 732b83e | 2014-06-09 13:20:04 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2009 Samsung Electronics |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Furquan Shaikh | 732b83e | 2014-06-09 13:20:04 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
Furquan Shaikh | 732b83e | 2014-06-09 13:20:04 -0700 | [diff] [blame] | 16 | #include <arch/io.h> |
| 17 | #include <boot/coreboot_tables.h> |
| 18 | #include <console/console.h> /* for __console definition */ |
Julius Werner | 96195ee | 2014-10-20 13:25:21 -0700 | [diff] [blame] | 19 | #include <console/uart.h> |
Furquan Shaikh | 732b83e | 2014-06-09 13:20:04 -0700 | [diff] [blame] | 20 | #include <drivers/uart/uart8250reg.h> |
Julius Werner | 96195ee | 2014-10-20 13:25:21 -0700 | [diff] [blame] | 21 | #include <stdint.h> |
Furquan Shaikh | 732b83e | 2014-06-09 13:20:04 -0700 | [diff] [blame] | 22 | |
| 23 | /* |
| 24 | * TODO: Use DRIVERS_UART_8250MEM driver instead. |
| 25 | * There is an issue in the IO call functions where x86 and ARM |
| 26 | * ordering is reversed. This 8250MEM driver uses the x86 convention. |
| 27 | * This driver can be replaced once the IO calls are sorted. |
| 28 | */ |
| 29 | struct tegra132_uart { |
| 30 | union { |
| 31 | uint32_t thr; // Transmit holding register. |
| 32 | uint32_t rbr; // Receive buffer register. |
| 33 | uint32_t dll; // Divisor latch lsb. |
| 34 | }; |
| 35 | union { |
| 36 | uint32_t ier; // Interrupt enable register. |
| 37 | uint32_t dlm; // Divisor latch msb. |
| 38 | }; |
| 39 | union { |
| 40 | uint32_t iir; // Interrupt identification register. |
| 41 | uint32_t fcr; // FIFO control register. |
| 42 | }; |
| 43 | uint32_t lcr; // Line control register. |
| 44 | uint32_t mcr; // Modem control register. |
| 45 | uint32_t lsr; // Line status register. |
| 46 | uint32_t msr; // Modem status register. |
| 47 | } __attribute__ ((packed)); |
| 48 | |
| 49 | static void tegra132_uart_tx_flush(struct tegra132_uart *uart_ptr); |
| 50 | static int tegra132_uart_tst_byte(struct tegra132_uart *uart_ptr); |
| 51 | |
| 52 | static void tegra132_uart_init(struct tegra132_uart *uart_ptr) |
| 53 | { |
| 54 | const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1 |
| 55 | |
| 56 | uint16_t divisor = (u16) uart_baudrate_divisor(default_baudrate(), |
| 57 | uart_platform_refclk(), 16); |
| 58 | |
| 59 | tegra132_uart_tx_flush(uart_ptr); |
| 60 | |
| 61 | // Disable interrupts. |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 62 | write8(&uart_ptr->ier, 0); |
Furquan Shaikh | 732b83e | 2014-06-09 13:20:04 -0700 | [diff] [blame] | 63 | // Force DTR and RTS to high. |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 64 | write8(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS); |
Furquan Shaikh | 732b83e | 2014-06-09 13:20:04 -0700 | [diff] [blame] | 65 | // Set line configuration, access divisor latches. |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 66 | write8(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config); |
Furquan Shaikh | 732b83e | 2014-06-09 13:20:04 -0700 | [diff] [blame] | 67 | // Set the divisor. |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 68 | write8(&uart_ptr->dll, divisor & 0xff); |
| 69 | write8(&uart_ptr->dlm, (divisor >> 8) & 0xff); |
Furquan Shaikh | 732b83e | 2014-06-09 13:20:04 -0700 | [diff] [blame] | 70 | // Hide the divisor latches. |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 71 | write8(&uart_ptr->lcr, line_config); |
Furquan Shaikh | 732b83e | 2014-06-09 13:20:04 -0700 | [diff] [blame] | 72 | // Enable FIFOs, and clear receive and transmit. |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame] | 73 | write8(&uart_ptr->fcr, UART8250_FCR_FIFO_EN | |
| 74 | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); |
Furquan Shaikh | 732b83e | 2014-06-09 13:20:04 -0700 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr) |
| 78 | { |
| 79 | if (!tegra132_uart_tst_byte(uart_ptr)) |
| 80 | return 0; |
| 81 | return read8(&uart_ptr->rbr); |
| 82 | } |
| 83 | |
| 84 | static void tegra132_uart_tx_byte(struct tegra132_uart *uart_ptr, unsigned char data) |
| 85 | { |
| 86 | while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE)); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 87 | write8(&uart_ptr->thr, data); |
Furquan Shaikh | 732b83e | 2014-06-09 13:20:04 -0700 | [diff] [blame] | 88 | } |
| 89 | |
| 90 | static void tegra132_uart_tx_flush(struct tegra132_uart *uart_ptr) |
| 91 | { |
| 92 | while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT)); |
| 93 | } |
| 94 | |
| 95 | static int tegra132_uart_tst_byte(struct tegra132_uart *uart_ptr) |
| 96 | { |
| 97 | return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR; |
| 98 | } |
| 99 | |
| 100 | /* FIXME: Add mainboard override */ |
| 101 | unsigned int uart_platform_refclk(void) |
| 102 | { |
| 103 | return 408000000; |
| 104 | } |
| 105 | |
| 106 | uintptr_t uart_platform_base(int idx) |
| 107 | { |
| 108 | /* Default to UART A */ |
| 109 | unsigned int base = 0x70006000; |
| 110 | /* UARTs A - E are mapped as index 0 - 4 */ |
| 111 | if ((idx < 5) && (idx >= 0)) { |
| 112 | if (idx != 1) { /* Not UART B */ |
| 113 | base += idx * 0x100; |
| 114 | } else { |
| 115 | base += 0x40; |
| 116 | } |
| 117 | } |
| 118 | return base; |
| 119 | } |
| 120 | |
| 121 | void uart_init(int idx) |
| 122 | { |
| 123 | struct tegra132_uart *uart_ptr = uart_platform_baseptr(idx); |
| 124 | tegra132_uart_init(uart_ptr); |
| 125 | } |
| 126 | |
| 127 | unsigned char uart_rx_byte(int idx) |
| 128 | { |
| 129 | struct tegra132_uart *uart_ptr = uart_platform_baseptr(idx); |
| 130 | return tegra132_uart_rx_byte(uart_ptr); |
| 131 | } |
| 132 | |
| 133 | void uart_tx_byte(int idx, unsigned char data) |
| 134 | { |
| 135 | struct tegra132_uart *uart_ptr = uart_platform_baseptr(idx); |
| 136 | tegra132_uart_tx_byte(uart_ptr, data); |
| 137 | } |
| 138 | |
| 139 | void uart_tx_flush(int idx) |
| 140 | { |
| 141 | struct tegra132_uart *uart_ptr = uart_platform_baseptr(idx); |
| 142 | tegra132_uart_tx_flush(uart_ptr); |
| 143 | } |
| 144 | |
Patrick Georgi | c96ff45 | 2015-05-07 12:29:13 +0200 | [diff] [blame] | 145 | #if ENV_RAMSTAGE |
Furquan Shaikh | 732b83e | 2014-06-09 13:20:04 -0700 | [diff] [blame] | 146 | void uart_fill_lb(void *data) |
| 147 | { |
| 148 | struct lb_serial serial; |
| 149 | serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; |
| 150 | serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); |
| 151 | serial.baud = default_baudrate(); |
Vadim Bendebury | 9dccf1c | 2015-01-09 16:54:19 -0800 | [diff] [blame] | 152 | serial.regwidth = 1; |
Furquan Shaikh | 732b83e | 2014-06-09 13:20:04 -0700 | [diff] [blame] | 153 | lb_add_serial(&serial, data); |
| 154 | |
| 155 | lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); |
| 156 | } |
| 157 | #endif |