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review.coreboot.org / coreboot / 9631016660423d0585a1 / src / soc / nvidia / tegra132 / uart.c
  1. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  2. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  3. c96ff45 nvidia/tegra132: we write tables in ramstage by Patrick Georgi · 9 years ago
  4. 9418476 arm(64): Manually clean up the mess left by write32() transition by Julius Werner · 10 years ago
  5. 2f37bd6 arm(64): Globally replace writel(v, a) with write32(a, v) by Julius Werner · 10 years ago
  6. d21a329 arm(64): Replace write32() and friends with writel() by Julius Werner · 10 years ago
  7. 9dccf1c uart: pass register width in the coreboot table by Vadim Bendebury · 10 years ago
  8. 96195ee tegra132: Change all SoC headers to <soc/headername.h> system by Julius Werner · 10 years ago
  9. 732b83e tegra132: Enable bootblock support in tegra132 including UART support by Furquan Shaikh · 10 years ago