Gabe Black | 08d5a89 | 2013-10-03 04:35:01 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Gabe Black | 08d5a89 | 2013-10-03 04:35:01 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef __SOC_NVIDIA_TEGRA_GPIO_H__ |
| 17 | #define __SOC_NVIDIA_TEGRA_GPIO_H__ |
| 18 | |
| 19 | #include <stdint.h> |
| 20 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 21 | #include "pinmux.h" |
Gabe Black | 08d5a89 | 2013-10-03 04:35:01 -0700 | [diff] [blame] | 22 | |
Julius Werner | eaa9c45 | 2014-09-24 15:40:49 -0700 | [diff] [blame] | 23 | typedef u32 gpio_t; |
| 24 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 25 | #define GPIO_PINMUX_SHIFT 16 |
| 26 | #define GPIO(name) ((gpio_t)(GPIO_##name##_INDEX | \ |
| 27 | (PINMUX_GPIO_##name << GPIO_PINMUX_SHIFT))) |
| 28 | |
Gabe Black | 08d5a89 | 2013-10-03 04:35:01 -0700 | [diff] [blame] | 29 | /* Functions to modify specific GPIO control values. */ |
| 30 | |
| 31 | enum gpio_mode { |
| 32 | GPIO_MODE_SPIO = 0, |
| 33 | GPIO_MODE_GPIO = 1 |
| 34 | }; |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 35 | void gpio_set_mode(gpio_t gpio, enum gpio_mode); |
| 36 | int gpio_get_mode(gpio_t gpio); |
Gabe Black | 08d5a89 | 2013-10-03 04:35:01 -0700 | [diff] [blame] | 37 | |
| 38 | // Lock a GPIO with extreme caution since they can't be unlocked. |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 39 | void gpio_set_lock(gpio_t gpio); |
| 40 | int gpio_get_lock(gpio_t gpio); |
Gabe Black | 08d5a89 | 2013-10-03 04:35:01 -0700 | [diff] [blame] | 41 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 42 | void gpio_set_out_enable(gpio_t gpio, int enable); |
| 43 | int gpio_get_out_enable(gpio_t gpio); |
Gabe Black | 08d5a89 | 2013-10-03 04:35:01 -0700 | [diff] [blame] | 44 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 45 | int gpio_get_out_value(gpio_t gpio); |
Gabe Black | 08d5a89 | 2013-10-03 04:35:01 -0700 | [diff] [blame] | 46 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 47 | int gpio_get_int_status(gpio_t gpio); |
Gabe Black | 08d5a89 | 2013-10-03 04:35:01 -0700 | [diff] [blame] | 48 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 49 | void gpio_set_int_enable(gpio_t gpio, int enable); |
| 50 | int gpio_get_int_enable(gpio_t gpio); |
Gabe Black | 08d5a89 | 2013-10-03 04:35:01 -0700 | [diff] [blame] | 51 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 52 | void gpio_set_int_level(gpio_t gpio, int high_rise, int edge, int delta); |
| 53 | void gpio_get_int_level(gpio_t gpio, int *high_rise, int *edge, int *delta); |
Gabe Black | 08d5a89 | 2013-10-03 04:35:01 -0700 | [diff] [blame] | 54 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 55 | void gpio_set_int_clear(gpio_t gpio); |
Gabe Black | 08d5a89 | 2013-10-03 04:35:01 -0700 | [diff] [blame] | 56 | |
Julius Werner | eaa9c45 | 2014-09-24 15:40:49 -0700 | [diff] [blame] | 57 | void gpio_output_open_drain(gpio_t gpio, int value); |
| 58 | |
Aaron Durbin | 401b3b6 | 2014-07-31 14:54:12 -0500 | [diff] [blame] | 59 | /* Hardware definitions. */ |
| 60 | |
| 61 | enum { |
| 62 | GPIO_GPIOS_PER_PORT = 8, |
| 63 | GPIO_PORTS_PER_BANK = 4, |
| 64 | GPIO_BANKS = 8, |
| 65 | |
| 66 | GPIO_GPIOS_PER_BANK = GPIO_GPIOS_PER_PORT * GPIO_PORTS_PER_BANK, |
| 67 | GPIO_GPIOS = GPIO_BANKS * GPIO_GPIOS_PER_BANK |
| 68 | }; |
| 69 | |
| 70 | static inline int gpio_index_to_bank(int index) |
| 71 | { |
| 72 | return index / GPIO_GPIOS_PER_BANK; |
| 73 | } |
| 74 | |
| 75 | static inline int gpio_index_to_port(int index) |
| 76 | { |
Aaron Durbin | 2f3a7fb | 2014-08-04 15:40:50 -0500 | [diff] [blame] | 77 | return (index % GPIO_GPIOS_PER_BANK) / GPIO_GPIOS_PER_PORT; |
Aaron Durbin | 401b3b6 | 2014-07-31 14:54:12 -0500 | [diff] [blame] | 78 | } |
| 79 | |
| 80 | static inline int gpio_to_bit(int index) |
| 81 | { |
| 82 | return index % GPIO_GPIOS_PER_PORT; |
| 83 | } |
| 84 | |
| 85 | struct gpio_bank { |
| 86 | // Values |
| 87 | u32 config[GPIO_PORTS_PER_BANK]; |
| 88 | u32 out_enable[GPIO_PORTS_PER_BANK]; |
| 89 | u32 out_value[GPIO_PORTS_PER_BANK]; |
| 90 | u32 in_value[GPIO_PORTS_PER_BANK]; |
| 91 | u32 int_status[GPIO_PORTS_PER_BANK]; |
| 92 | u32 int_enable[GPIO_PORTS_PER_BANK]; |
| 93 | u32 int_level[GPIO_PORTS_PER_BANK]; |
| 94 | u32 int_clear[GPIO_PORTS_PER_BANK]; |
| 95 | |
| 96 | // Masks |
| 97 | u32 config_mask[GPIO_PORTS_PER_BANK]; |
| 98 | u32 out_enable_mask[GPIO_PORTS_PER_BANK]; |
| 99 | u32 out_value_mask[GPIO_PORTS_PER_BANK]; |
| 100 | u32 in_value_mask[GPIO_PORTS_PER_BANK]; |
| 101 | u32 int_status_mask[GPIO_PORTS_PER_BANK]; |
| 102 | u32 int_enable_mask[GPIO_PORTS_PER_BANK]; |
| 103 | u32 int_level_mask[GPIO_PORTS_PER_BANK]; |
| 104 | u32 int_clear_mask[GPIO_PORTS_PER_BANK]; |
| 105 | }; |
| 106 | |
Gabe Black | 08d5a89 | 2013-10-03 04:35:01 -0700 | [diff] [blame] | 107 | #endif /* __SOC_NVIDIA_TEGRA_GPIO_H__ */ |