Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <arch/io.h> |
| 17 | #include <console/console.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <device/pci_ids.h> |
| 20 | #include <stdlib.h> |
| 21 | #include <string.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 22 | #include <soc/pci_devs.h> |
| 23 | #include <soc/me.h> |
Duncan Laurie | a7d8ea8 | 2014-08-26 13:49:24 -0700 | [diff] [blame] | 24 | #include <delay.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 25 | |
Duncan Laurie | 0b92a5e | 2014-10-03 15:34:09 -0700 | [diff] [blame] | 26 | static inline void me_read_dword_ptr(void *ptr, int offset) |
| 27 | { |
| 28 | u32 dword = pci_read_config32(PCH_DEV_ME, offset); |
| 29 | memcpy(ptr, &dword, sizeof(dword)); |
| 30 | } |
| 31 | |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 32 | #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) |
| 33 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 34 | /* HFS1[3:0] Current Working State Values */ |
| 35 | static const char *me_cws_values[] = { |
| 36 | [ME_HFS_CWS_RESET] = "Reset", |
| 37 | [ME_HFS_CWS_INIT] = "Initializing", |
| 38 | [ME_HFS_CWS_REC] = "Recovery", |
| 39 | [3] = "Unknown (3)", |
| 40 | [4] = "Unknown (4)", |
| 41 | [ME_HFS_CWS_NORMAL] = "Normal", |
| 42 | [ME_HFS_CWS_WAIT] = "Platform Disable Wait", |
| 43 | [ME_HFS_CWS_TRANS] = "OP State Transition", |
| 44 | [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In", |
| 45 | [9] = "Unknown (9)", |
| 46 | [10] = "Unknown (10)", |
| 47 | [11] = "Unknown (11)", |
| 48 | [12] = "Unknown (12)", |
| 49 | [13] = "Unknown (13)", |
| 50 | [14] = "Unknown (14)", |
| 51 | [15] = "Unknown (15)", |
| 52 | }; |
| 53 | |
| 54 | /* HFS1[8:6] Current Operation State Values */ |
| 55 | static const char *me_opstate_values[] = { |
| 56 | [ME_HFS_STATE_PREBOOT] = "Preboot", |
| 57 | [ME_HFS_STATE_M0_UMA] = "M0 with UMA", |
| 58 | [ME_HFS_STATE_M3] = "M3 without UMA", |
| 59 | [ME_HFS_STATE_M0] = "M0 without UMA", |
| 60 | [ME_HFS_STATE_BRINGUP] = "Bring up", |
| 61 | [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" |
| 62 | }; |
| 63 | |
| 64 | /* HFS[19:16] Current Operation Mode Values */ |
| 65 | static const char *me_opmode_values[] = { |
| 66 | [ME_HFS_MODE_NORMAL] = "Normal", |
| 67 | [ME_HFS_MODE_DEBUG] = "Debug", |
| 68 | [ME_HFS_MODE_DIS] = "Soft Temporary Disable", |
| 69 | [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", |
| 70 | [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" |
| 71 | }; |
| 72 | |
| 73 | /* HFS[15:12] Error Code Values */ |
| 74 | static const char *me_error_values[] = { |
| 75 | [ME_HFS_ERROR_NONE] = "No Error", |
| 76 | [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", |
| 77 | [ME_HFS_ERROR_IMAGE] = "Image Failure", |
| 78 | [ME_HFS_ERROR_DEBUG] = "Debug Failure" |
| 79 | }; |
| 80 | |
| 81 | /* HFS2[31:28] ME Progress Code */ |
| 82 | static const char *me_progress_values[] = { |
| 83 | [ME_HFS2_PHASE_ROM] = "ROM Phase", |
| 84 | [ME_HFS2_PHASE_BUP] = "BUP Phase", |
| 85 | [ME_HFS2_PHASE_UKERNEL] = "uKernel Phase", |
| 86 | [ME_HFS2_PHASE_POLICY] = "Policy Module", |
| 87 | [ME_HFS2_PHASE_MODULE_LOAD] = "Module Loading", |
| 88 | [ME_HFS2_PHASE_UNKNOWN] = "Unknown", |
| 89 | [ME_HFS2_PHASE_HOST_COMM] = "Host Communication" |
| 90 | }; |
| 91 | |
| 92 | /* HFS2[27:24] Power Management Event */ |
| 93 | static const char *me_pmevent_values[] = { |
| 94 | [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = |
| 95 | "Clean Moff->Mx wake", |
| 96 | [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = |
| 97 | "Moff->Mx wake after an error", |
| 98 | [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = |
| 99 | "Clean global reset", |
| 100 | [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = |
| 101 | "Global reset after an error", |
| 102 | [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = |
| 103 | "Clean Intel ME reset", |
| 104 | [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = |
| 105 | "Intel ME reset due to exception", |
| 106 | [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = |
| 107 | "Pseudo-global reset", |
| 108 | [ME_HFS2_PMEVENT_S0MO_SXM3] = |
| 109 | "S0/M0->Sx/M3", |
| 110 | [ME_HFS2_PMEVENT_SXM3_S0M0] = |
| 111 | "Sx/M3->S0/M0", |
| 112 | [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = |
| 113 | "Non-power cycle reset", |
| 114 | [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = |
| 115 | "Power cycle reset through M3", |
| 116 | [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = |
| 117 | "Power cycle reset through Moff", |
| 118 | [ME_HFS2_PMEVENT_SXMX_SXMOFF] = |
| 119 | "Sx/Mx->Sx/Moff" |
| 120 | }; |
| 121 | |
| 122 | /* Progress Code 0 states */ |
| 123 | static const char *me_progress_rom_values[] = { |
| 124 | [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", |
| 125 | [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE" |
| 126 | }; |
| 127 | |
| 128 | /* Progress Code 1 states */ |
| 129 | static const char *me_progress_bup_values[] = { |
| 130 | [ME_HFS2_STATE_BUP_INIT] = |
| 131 | "Initialization starts", |
| 132 | [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = |
| 133 | "Disable the host wake event", |
| 134 | [ME_HFS2_STATE_BUP_FLOW_DET] = |
| 135 | "Flow determination start process", |
| 136 | [ME_HFS2_STATE_BUP_VSCC_ERR] = |
| 137 | "Error reading/matching the VSCC table in the descriptor", |
| 138 | [ME_HFS2_STATE_BUP_CHECK_STRAP] = |
| 139 | "Check to see if straps say ME DISABLED", |
| 140 | [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = |
| 141 | "Timeout waiting for PWROK", |
| 142 | [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = |
| 143 | "Possibly handle BUP manufacturing override strap", |
| 144 | [ME_HFS2_STATE_BUP_M3] = |
| 145 | "Bringup in M3", |
| 146 | [ME_HFS2_STATE_BUP_M0] = |
| 147 | "Bringup in M0", |
| 148 | [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = |
| 149 | "Flow detection error", |
| 150 | [ME_HFS2_STATE_BUP_M3_CLK_ERR] = |
| 151 | "M3 clock switching error", |
| 152 | [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = |
| 153 | "Host error - CPU reset timeout, DID timeout, memory missing", |
| 154 | [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = |
| 155 | "M3 kernel load", |
| 156 | [ME_HFS2_STATE_BUP_T32_MISSING] = |
| 157 | "T34 missing - cannot program ICC", |
| 158 | [ME_HFS2_STATE_BUP_WAIT_DID] = |
| 159 | "Waiting for DID BIOS message", |
| 160 | [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = |
| 161 | "Waiting for DID BIOS message failure", |
| 162 | [ME_HFS2_STATE_BUP_DID_NO_FAIL] = |
| 163 | "DID reported no error", |
| 164 | [ME_HFS2_STATE_BUP_ENABLE_UMA] = |
| 165 | "Enabling UMA", |
| 166 | [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = |
| 167 | "Enabling UMA error", |
| 168 | [ME_HFS2_STATE_BUP_SEND_DID_ACK] = |
| 169 | "Sending DID Ack to BIOS", |
| 170 | [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = |
| 171 | "Sending DID Ack to BIOS error", |
| 172 | [ME_HFS2_STATE_BUP_M0_CLK] = |
| 173 | "Switching clocks in M0", |
| 174 | [ME_HFS2_STATE_BUP_M0_CLK_ERR] = |
| 175 | "Switching clocks in M0 error", |
| 176 | [ME_HFS2_STATE_BUP_TEMP_DIS] = |
| 177 | "ME in temp disable", |
| 178 | [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = |
| 179 | "M0 kernel load", |
| 180 | }; |
| 181 | |
| 182 | /* Progress Code 3 states */ |
| 183 | static const char *me_progress_policy_values[] = { |
Martin Roth | de7ed6f | 2014-12-07 14:58:18 -0700 | [diff] [blame] | 184 | [ME_HFS2_STATE_POLICY_ENTRY] = "Entry into Policy Module", |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 185 | [ME_HFS2_STATE_POLICY_RCVD_S3] = "Received S3 entry", |
| 186 | [ME_HFS2_STATE_POLICY_RCVD_S4] = "Received S4 entry", |
| 187 | [ME_HFS2_STATE_POLICY_RCVD_S5] = "Received S5 entry", |
| 188 | [ME_HFS2_STATE_POLICY_RCVD_UPD] = "Received UPD entry", |
| 189 | [ME_HFS2_STATE_POLICY_RCVD_PCR] = "Received PCR entry", |
| 190 | [ME_HFS2_STATE_POLICY_RCVD_NPCR] = "Received NPCR entry", |
| 191 | [ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE] = "Received host wake", |
| 192 | [ME_HFS2_STATE_POLICY_RCVD_AC_DC] = "Received AC<>DC switch", |
| 193 | [ME_HFS2_STATE_POLICY_RCVD_DID] = "Received DRAM Init Done", |
| 194 | [ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND] = |
| 195 | "VSCC Data not found for flash device", |
| 196 | [ME_HFS2_STATE_POLICY_VSCC_INVALID] = |
| 197 | "VSCC Table is not valid", |
| 198 | [ME_HFS2_STATE_POLICY_FPB_ERR] = |
| 199 | "Flash Partition Boundary is outside address space", |
| 200 | [ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR] = |
| 201 | "ME cannot access the chipset descriptor region", |
| 202 | [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = |
| 203 | "Required VSCC values for flash parts do not match", |
| 204 | }; |
| 205 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 206 | void intel_me_status(void) |
| 207 | { |
| 208 | struct me_hfs _hfs, *hfs = &_hfs; |
| 209 | struct me_hfs2 _hfs2, *hfs2 = &_hfs2; |
| 210 | |
| 211 | me_read_dword_ptr(hfs, PCI_ME_HFS); |
| 212 | me_read_dword_ptr(hfs2, PCI_ME_HFS2); |
| 213 | |
| 214 | /* Check Current States */ |
| 215 | printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", |
| 216 | hfs->fpt_bad ? "BAD" : "OK"); |
| 217 | printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", |
| 218 | hfs->ft_bup_ld_flr ? "YES" : "NO"); |
| 219 | printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", |
| 220 | hfs->fw_init_complete ? "YES" : "NO"); |
| 221 | printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", |
| 222 | hfs->mfg_mode ? "YES" : "NO"); |
| 223 | printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", |
| 224 | hfs->boot_options_present ? "YES" : "NO"); |
| 225 | printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", |
| 226 | hfs->update_in_progress ? "YES" : "NO"); |
| 227 | printk(BIOS_DEBUG, "ME: Current Working State : %s\n", |
| 228 | me_cws_values[hfs->working_state]); |
| 229 | printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", |
| 230 | me_opstate_values[hfs->operation_state]); |
| 231 | printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", |
| 232 | me_opmode_values[hfs->operation_mode]); |
| 233 | printk(BIOS_DEBUG, "ME: Error Code : %s\n", |
| 234 | me_error_values[hfs->error_code]); |
| 235 | printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", |
| 236 | me_progress_values[hfs2->progress_code]); |
| 237 | printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", |
| 238 | me_pmevent_values[hfs2->current_pmevent]); |
| 239 | |
| 240 | printk(BIOS_DEBUG, "ME: Progress Phase State : "); |
| 241 | switch (hfs2->progress_code) { |
| 242 | case ME_HFS2_PHASE_ROM: /* ROM Phase */ |
| 243 | printk(BIOS_DEBUG, "%s", |
| 244 | me_progress_rom_values[hfs2->current_state]); |
| 245 | break; |
| 246 | |
Duncan Laurie | 32dfd06 | 2014-10-09 16:14:39 -0700 | [diff] [blame] | 247 | case ME_HFS2_PHASE_UKERNEL: /* uKernel Phase */ |
| 248 | printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); |
| 249 | break; |
| 250 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 251 | case ME_HFS2_PHASE_BUP: /* Bringup Phase */ |
| 252 | if (hfs2->current_state < ARRAY_SIZE(me_progress_bup_values) |
| 253 | && me_progress_bup_values[hfs2->current_state]) |
| 254 | printk(BIOS_DEBUG, "%s", |
| 255 | me_progress_bup_values[hfs2->current_state]); |
| 256 | else |
| 257 | printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); |
| 258 | break; |
| 259 | |
| 260 | case ME_HFS2_PHASE_POLICY: /* Policy Module Phase */ |
| 261 | if (hfs2->current_state < ARRAY_SIZE(me_progress_policy_values) |
| 262 | && me_progress_policy_values[hfs2->current_state]) |
| 263 | printk(BIOS_DEBUG, "%s", |
| 264 | me_progress_policy_values[hfs2->current_state]); |
| 265 | else |
| 266 | printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); |
| 267 | break; |
| 268 | |
| 269 | case ME_HFS2_PHASE_HOST_COMM: /* Host Communication Phase */ |
| 270 | if (!hfs2->current_state) |
| 271 | printk(BIOS_DEBUG, "Host communication established"); |
| 272 | else |
| 273 | printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); |
| 274 | break; |
| 275 | |
| 276 | default: |
Duncan Laurie | 32dfd06 | 2014-10-09 16:14:39 -0700 | [diff] [blame] | 277 | printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x", |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 278 | hfs2->progress_code, hfs2->current_state); |
| 279 | } |
| 280 | printk(BIOS_DEBUG, "\n"); |
| 281 | } |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 282 | #endif |
Duncan Laurie | a7d8ea8 | 2014-08-26 13:49:24 -0700 | [diff] [blame] | 283 | |
| 284 | void intel_me_hsio_version(uint16_t *version, uint16_t *checksum) |
| 285 | { |
| 286 | int count; |
| 287 | u32 hsiover; |
| 288 | struct me_hfs hfs; |
| 289 | |
| 290 | /* Query for HSIO version, overloads H_GS and HFS */ |
| 291 | pci_write_config32(PCH_DEV_ME, PCI_ME_H_GS, |
| 292 | ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER); |
| 293 | |
| 294 | /* Must wait for ME acknowledgement */ |
| 295 | for (count = ME_RETRY; count > 0; --count) { |
| 296 | me_read_dword_ptr(&hfs, PCI_ME_HFS); |
| 297 | if (hfs.bios_msg_ack) |
| 298 | break; |
| 299 | udelay(ME_DELAY); |
| 300 | } |
| 301 | if (!count) { |
| 302 | printk(BIOS_ERR, "ERROR: ME failed to respond\n"); |
| 303 | return; |
| 304 | } |
| 305 | |
| 306 | /* HSIO version should be in HFS_5 */ |
| 307 | hsiover = pci_read_config32(PCH_DEV_ME, PCI_ME_HFS5); |
| 308 | *version = hsiover >> 16; |
| 309 | *checksum = hsiover & 0xffff; |
| 310 | |
| 311 | printk(BIOS_DEBUG, "ME: HSIO Version : %d (CRC 0x%04x)\n", |
| 312 | *version, *checksum); |
| 313 | |
| 314 | /* Reset registers to normal behavior */ |
| 315 | pci_write_config32(PCH_DEV_ME, PCI_ME_H_GS, |
| 316 | ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER); |
| 317 | } |