Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corp. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/cpu.h> |
| 18 | #include <arch/acpi.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 19 | #include <bootstate.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 20 | #include <cbmem.h> |
| 21 | #include <console/console.h> |
| 22 | #include <cpu/intel/microcode.h> |
| 23 | #include <cpu/x86/cr.h> |
| 24 | #include <cpu/x86/msr.h> |
| 25 | #include <device/device.h> |
| 26 | #include <device/pci_def.h> |
| 27 | #include <device/pci_ops.h> |
Aaron Durbin | 789f2b6 | 2015-09-09 17:05:06 -0500 | [diff] [blame] | 28 | #include <fsp/util.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 29 | #include <romstage_handoff.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 30 | #include <soc/gpio.h> |
| 31 | #include <soc/lpc.h> |
| 32 | #include <soc/msr.h> |
| 33 | #include <soc/nvs.h> |
| 34 | #include <soc/pattrs.h> |
| 35 | #include <soc/pci_devs.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 36 | #include <soc/pm.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 37 | #include <soc/ramstage.h> |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 38 | #include <soc/intel/common/acpi.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 39 | #include <boardid.h> |
| 40 | #include <stdlib.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 41 | |
| 42 | #define SHOW_PATTRS 1 |
| 43 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 44 | struct pattrs __global_pattrs; |
| 45 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 46 | static void detect_num_cpus(struct pattrs *attrs) |
| 47 | { |
| 48 | int ecx = 0; |
| 49 | |
| 50 | while (1) { |
| 51 | struct cpuid_result leaf_b; |
| 52 | |
| 53 | leaf_b = cpuid_ext(0xb, ecx); |
| 54 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 55 | /* |
| 56 | * The SOC doesn't have hyperthreading so just determine the |
| 57 | * number of cores by from level type (ecx[15:8] == * 2). |
| 58 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 59 | if ((leaf_b.ecx & 0xff00) == 0x0200) { |
| 60 | attrs->num_cpus = leaf_b.ebx & 0xffff; |
| 61 | break; |
| 62 | } |
| 63 | ecx++; |
| 64 | } |
| 65 | } |
| 66 | |
| 67 | static inline void fill_in_msr(msr_t *msr, int idx) |
| 68 | { |
| 69 | *msr = rdmsr(idx); |
| 70 | if (SHOW_PATTRS) { |
| 71 | printk(BIOS_DEBUG, "msr(%x) = %08x%08x\n", |
| 72 | idx, msr->hi, msr->lo); |
| 73 | } |
| 74 | } |
| 75 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 76 | static const char * const stepping_str[] = { |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 77 | "A0", "A1", "B0", "B1", "B2", "B3", "C0" |
| 78 | }; |
| 79 | |
| 80 | static void fill_in_pattrs(void) |
| 81 | { |
| 82 | device_t dev; |
| 83 | msr_t msr; |
| 84 | struct pattrs *attrs = (struct pattrs *)pattrs_get(); |
| 85 | |
| 86 | attrs->cpuid = cpuid_eax(1); |
| 87 | dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); |
| 88 | attrs->revid = pci_read_config8(dev, REVID); |
| 89 | /* The revision to stepping IDs have two values per metal stepping. */ |
| 90 | if (attrs->revid >= RID_C_STEPPING_START) { |
| 91 | attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2; |
| 92 | attrs->stepping += STEP_C0; |
| 93 | } else if (attrs->revid >= RID_B_STEPPING_START) { |
| 94 | attrs->stepping = (attrs->revid - RID_B_STEPPING_START) / 2; |
| 95 | attrs->stepping += STEP_B0; |
| 96 | } else { |
| 97 | attrs->stepping = (attrs->revid - RID_A_STEPPING_START) / 2; |
| 98 | attrs->stepping += STEP_A0; |
| 99 | } |
| 100 | |
| 101 | attrs->microcode_patch = intel_microcode_find(); |
| 102 | attrs->address_bits = cpuid_eax(0x80000008) & 0xff; |
| 103 | detect_num_cpus(attrs); |
| 104 | |
| 105 | if (SHOW_PATTRS) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 106 | printk(BIOS_DEBUG, "Cpuid %08x cpus %d rid %02x step %s\n", |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 107 | attrs->cpuid, attrs->num_cpus, attrs->revid, |
| 108 | (attrs->stepping >= ARRAY_SIZE(stepping_str)) ? "??" : |
| 109 | stepping_str[attrs->stepping]); |
| 110 | } |
| 111 | |
| 112 | fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); |
| 113 | fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); |
| 114 | |
| 115 | /* Set IA core speed ratio and voltages */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 116 | fill_in_msr(&msr, MSR_IACORE_RATIOS); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 117 | attrs->iacore_ratios[IACORE_MIN] = msr.lo & 0x7f; |
| 118 | attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f; |
| 119 | attrs->iacore_ratios[IACORE_MAX] = (msr.lo >> 16) & 0x7f; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 120 | fill_in_msr(&msr, MSR_IACORE_TURBO_RATIOS); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 121 | attrs->iacore_ratios[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ |
| 122 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 123 | fill_in_msr(&msr, MSR_IACORE_VIDS); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 124 | attrs->iacore_vids[IACORE_MIN] = msr.lo & 0x7f; |
| 125 | attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f; |
| 126 | attrs->iacore_vids[IACORE_MAX] = (msr.lo >> 16) & 0x7f; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 127 | fill_in_msr(&msr, MSR_IACORE_TURBO_VIDS); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 128 | attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ |
| 129 | |
| 130 | /* Set bus clock speed */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 131 | attrs->bclk_khz = BUS_FREQ_KHZ; |
| 132 | } |
| 133 | |
| 134 | static inline void set_acpi_sleep_type(int val) |
| 135 | { |
| 136 | #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) |
| 137 | acpi_slp_type = val; |
| 138 | #endif |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 139 | } |
| 140 | |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 141 | /* Save wake source information for calculating ACPI _SWS values */ |
| 142 | int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 143 | { |
| 144 | struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 145 | static uint32_t gpe0_sts; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 146 | |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 147 | *pm1 = ps->pm1_sts & ps->pm1_en; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 148 | |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 149 | gpe0_sts = ps->gpe0_sts & ps->gpe0_en; |
| 150 | *gpe0 = &gpe0_sts; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 151 | |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 152 | return 1; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | static void s3_resume_prepare(void) |
| 156 | { |
| 157 | global_nvs_t *gnvs; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 158 | struct romstage_handoff *romstage_handoff; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 159 | |
| 160 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 161 | |
| 162 | romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); |
| 163 | if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { |
| 164 | if (gnvs != NULL) |
| 165 | memset(gnvs, 0, sizeof(global_nvs_t)); |
| 166 | set_acpi_sleep_type(0); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 167 | return; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 168 | } |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 169 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 170 | set_acpi_sleep_type(3); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 171 | } |
| 172 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 173 | static void set_board_id(void) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 174 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 175 | global_nvs_t *gnvs; |
| 176 | |
| 177 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 178 | if (!gnvs) { |
| 179 | printk(BIOS_ERR, "Unable to locate Global NVS\n"); |
| 180 | return; |
| 181 | } |
| 182 | gnvs->bdid = board_id(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 183 | } |
| 184 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 185 | void soc_init_pre_device(struct soc_intel_braswell_config *config) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 186 | { |
| 187 | struct soc_gpio_config *gpio_config; |
| 188 | |
| 189 | fill_in_pattrs(); |
| 190 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 191 | /* Allow for SSE instructions to be executed. */ |
| 192 | write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); |
| 193 | |
| 194 | /* Indicate S3 resume to rest of ramstage. */ |
| 195 | s3_resume_prepare(); |
| 196 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 197 | /* Perform silicon specific init. */ |
| 198 | intel_silicon_init(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 199 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 200 | set_board_id(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 201 | /* Get GPIO initial states from mainboard */ |
| 202 | gpio_config = mainboard_get_gpios(); |
| 203 | setup_soc_gpios(gpio_config, config->enable_xdp_tap); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 204 | } |