Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2010 Nils Jacobs |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
Paul Menzel | a8ae1c6 | 2013-02-20 13:21:20 +0100 | [diff] [blame] | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 14 | * GNU General Public License for more details. |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 17 | #include <console/console.h> |
| 18 | #include <arch/io.h> |
| 19 | #include <stdint.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <stdlib.h> |
| 24 | #include <string.h> |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 25 | #include "northbridge.h" |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 26 | #include <cpu/x86/msr.h> |
| 27 | #include <cpu/x86/cache.h> |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 28 | #include <cpu/amd/vr.h> |
Corey Osgood | e562f72 | 2008-12-19 03:36:48 +0000 | [diff] [blame] | 29 | #include <cpu/cpu.h> |
Marc Jones | 08da4f1 | 2007-05-04 19:09:01 +0000 | [diff] [blame] | 30 | #include "../../../southbridge/amd/cs5536/cs5536.h" |
Ronald G. Minnich | 36c00aa | 2006-04-18 22:40:53 +0000 | [diff] [blame] | 31 | |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 32 | void print_conf(void); |
| 33 | |
| 34 | /* Print the platform configuration - do before PCI init or it will not |
| 35 | * work right. |
| 36 | */ |
| 37 | void print_conf(void) |
| 38 | { |
| 39 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR |
| 40 | int i; |
| 41 | unsigned long iol; |
| 42 | msr_t msr; |
| 43 | |
| 44 | int cpu_msr_defs[] = { CPU_IM_CONFIG, CPU_DM_CONFIG0, |
| 45 | CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, |
| 46 | CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM, |
| 47 | GLCP_DELAY_CONTROLS, GL_END |
| 48 | }; |
| 49 | |
| 50 | int gliu0_msr_defs[] = { GLIU0_P2D_BM_0, GLIU0_P2D_BM_1, |
| 51 | GLIU0_P2D_BM_2, GLIU0_P2D_BM_3, GLIU0_P2D_BM_4, |
| 52 | GLIU0_P2D_BM_5, GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, |
| 53 | GLIU0_P2D_R_0, GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, |
| 54 | GLIU0_P2D_RO_2, GLIU0_P2D_SC_0, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, |
| 55 | GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, |
| 56 | GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5, |
| 57 | GLIU0_GLD_MSR_COH, GL_END |
| 58 | }; |
| 59 | |
| 60 | int gliu1_msr_defs[] = { GLIU1_P2D_BM_0, GLIU1_P2D_BM_1, |
| 61 | GLIU1_P2D_BM_2, GLIU1_P2D_BM_3, GLIU1_P2D_BM_4, |
| 62 | GLIU1_P2D_BM_5, GLIU1_P2D_BM_6, GLIU1_P2D_BM_7, |
| 63 | GLIU1_P2D_BM_8, GLIU1_P2D_R_0, GLIU1_P2D_R_1, |
| 64 | GLIU1_P2D_R_2, GLIU1_P2D_R_3, GLIU1_P2D_SC_0, |
| 65 | GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0, |
| 66 | GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3, GLIU1_IOD_SC_4, |
| 67 | GLIU1_IOD_SC_5, GLIU1_GLD_MSR_COH, GL_END |
| 68 | }; |
| 69 | |
| 70 | int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, |
| 71 | CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END |
| 72 | }; |
| 73 | |
| 74 | int lbar_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, GL_END |
| 75 | }; |
| 76 | |
| 77 | int irq_msr[] = { MDD_IRQM_YLOW, MDD_IRQM_YHIGH, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, |
| 78 | MDD_IRQM_PRIM, GL_END |
| 79 | }; |
| 80 | |
| 81 | int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, |
| 82 | GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, |
| 83 | GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END |
| 84 | }; |
| 85 | |
| 86 | int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, |
| 87 | MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6, |
| 88 | MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END |
| 89 | }; |
| 90 | |
| 91 | printk(BIOS_DEBUG, "---------- CPU ------------\n"); |
| 92 | |
| 93 | for (i = 0; cpu_msr_defs[i] != GL_END; i++) { |
| 94 | msr = rdmsr(cpu_msr_defs[i]); |
| 95 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", |
| 96 | cpu_msr_defs[i], msr.hi, msr.lo); |
| 97 | } |
| 98 | |
| 99 | printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n"); |
| 100 | |
| 101 | for (i = 0; gliu0_msr_defs[i] != GL_END; i++) { |
| 102 | msr = rdmsr(gliu0_msr_defs[i]); |
| 103 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", |
| 104 | gliu0_msr_defs[i], msr.hi, msr.lo); |
| 105 | } |
| 106 | |
| 107 | printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n"); |
| 108 | |
| 109 | for (i = 0; gliu1_msr_defs[i] != GL_END; i++) { |
| 110 | msr = rdmsr(gliu1_msr_defs[i]); |
| 111 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", |
| 112 | gliu1_msr_defs[i], msr.hi, msr.lo); |
| 113 | } |
| 114 | |
| 115 | printk(BIOS_DEBUG, "---------- RCONF ------------\n"); |
| 116 | |
| 117 | for (i = 0; rconf_msr[i] != GL_END; i++) { |
| 118 | msr = rdmsr(rconf_msr[i]); |
| 119 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], |
| 120 | msr.hi, msr.lo); |
| 121 | } |
| 122 | |
| 123 | printk(BIOS_DEBUG, "---------- VARIA ------------\n"); |
| 124 | msr = rdmsr(ATA_SB_IDE_CFG); |
| 125 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", ATA_SB_IDE_CFG, msr.hi, |
| 126 | msr.lo); |
| 127 | |
| 128 | msr = rdmsr(MDD_LEG_IO); |
| 129 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_LEG_IO, msr.hi, |
| 130 | msr.lo); |
| 131 | |
| 132 | msr = rdmsr(MDD_PIN_OPT); |
| 133 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_PIN_OPT, msr.hi, |
| 134 | msr.lo); |
| 135 | |
| 136 | printk(BIOS_DEBUG, "---------- PCI ------------\n"); |
| 137 | |
| 138 | for (i = 0; pci_msr[i] != GL_END; i++) { |
| 139 | msr = rdmsr(pci_msr[i]); |
| 140 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], |
| 141 | msr.hi, msr.lo); |
| 142 | } |
| 143 | |
| 144 | printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n"); |
| 145 | |
| 146 | for (i = 0; dma_msr[i] != GL_END; i++) { |
| 147 | msr = rdmsr(dma_msr[i]); |
| 148 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], |
| 149 | msr.hi, msr.lo); |
| 150 | } |
| 151 | |
| 152 | printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n"); |
| 153 | |
| 154 | for (i = 0; irq_msr[i] != GL_END; i++) { |
| 155 | msr = rdmsr(irq_msr[i]); |
| 156 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", irq_msr[i], |
| 157 | msr.hi, msr.lo); |
| 158 | } |
| 159 | |
| 160 | printk(BIOS_DEBUG, "---------- DIVIL LBAR -----------\n"); |
| 161 | |
| 162 | for (i = 0; lbar_msr[i] != GL_END; i++) { |
| 163 | msr = rdmsr(lbar_msr[i]); |
| 164 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", lbar_msr[i], |
| 165 | msr.hi, msr.lo); |
| 166 | } |
| 167 | |
| 168 | iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE); |
| 169 | printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", |
| 170 | GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol); |
| 171 | iol = inl(GPIOL_EVENTS_ENABLE); |
| 172 | printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", |
| 173 | GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol); |
| 174 | iol = inl(GPIOL_INPUT_INVERT_ENABLE); |
| 175 | printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", |
| 176 | GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol); |
| 177 | iol = inl(GPIO_MAPPER_X); |
| 178 | printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X, |
| 179 | iol); |
| 180 | #endif /* CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR */ |
| 181 | } |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 182 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 183 | /* todo: add a resource record. We don't do this here because this may be called when |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 184 | * very little of the platform is actually working. |
| 185 | */ |
| 186 | int sizeram(void) |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 187 | { |
| 188 | msr_t msr; |
Ronald G. Minnich | cd6985b | 2006-03-21 23:24:33 +0000 | [diff] [blame] | 189 | int sizem = 0; |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 190 | unsigned short dimm; |
| 191 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 192 | /* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */ |
Nils Jacobs | 3344743 | 2010-12-26 05:16:47 +0000 | [diff] [blame] | 193 | msr = rdmsr(MC_CF07_DATA); |
| 194 | printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo); |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 195 | |
| 196 | /* dimm 0 */ |
| 197 | dimm = msr.hi; |
| 198 | /* installed? */ |
| 199 | if ((dimm & 7) != 7) |
| 200 | sizem = (1 << ((dimm >> 12)-1)) * 8; |
| 201 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 202 | /* dimm 1 */ |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 203 | dimm = msr.hi >> 16; |
| 204 | /* installed? */ |
| 205 | if ((dimm & 7) != 7) |
| 206 | sizem += (1 << ((dimm >> 12)-1)) * 8; |
| 207 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 208 | printk(BIOS_DEBUG, "sizeram: sizem 0x%x\n", sizem); |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 209 | return sizem; |
| 210 | } |
| 211 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 212 | static void enable_shadow(device_t dev) |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 213 | { |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 214 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 215 | } |
| 216 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 217 | static void northbridge_init(device_t dev) |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 218 | { |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 219 | printk(BIOS_SPEW, ">> Entering northbridge: %s()\n", __func__); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 220 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 221 | enable_shadow(dev); |
| 222 | } |
| 223 | |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 224 | static void northbridge_set_resources(struct device *dev) |
Ronald G. Minnich | 08af3f5 | 2006-08-09 02:21:49 +0000 | [diff] [blame] | 225 | { |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 226 | uint8_t line; |
| 227 | |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 228 | struct bus *bus; |
Stefan Reinauer | 4154c66 | 2010-04-14 10:12:23 +0000 | [diff] [blame] | 229 | |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 230 | for(bus = dev->link_list; bus; bus = bus->next) { |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 231 | if (bus->children) { |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 232 | printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n", |
| 233 | bus->secondary); |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 234 | assign_resources(bus); |
| 235 | } |
| 236 | } |
Ronald G. Minnich | 08af3f5 | 2006-08-09 02:21:49 +0000 | [diff] [blame] | 237 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 238 | /* set a default latency timer */ |
| 239 | pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); |
Ronald G. Minnich | 08af3f5 | 2006-08-09 02:21:49 +0000 | [diff] [blame] | 240 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 241 | /* set a default secondary latency timer */ |
| 242 | if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { |
| 243 | pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40); |
| 244 | } |
Ronald G. Minnich | 08af3f5 | 2006-08-09 02:21:49 +0000 | [diff] [blame] | 245 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 246 | /* zero the irq settings */ |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 247 | line = pci_read_config8(dev, PCI_INTERRUPT_PIN); |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 248 | if (line) { |
| 249 | pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); |
| 250 | } |
| 251 | /* set the cache line size, so far 64 bytes is good for everyone */ |
| 252 | pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); |
Ronald G. Minnich | 08af3f5 | 2006-08-09 02:21:49 +0000 | [diff] [blame] | 253 | } |
| 254 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 255 | static struct device_operations northbridge_operations = { |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 256 | .read_resources = pci_dev_read_resources, |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 257 | .set_resources = northbridge_set_resources, |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 258 | .enable_resources = pci_dev_enable_resources, |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 259 | .init = northbridge_init, |
| 260 | .enable = 0, |
| 261 | .ops_pci = 0, |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 262 | }; |
| 263 | |
Stefan Reinauer | f1cf1f7 | 2007-10-24 09:08:58 +0000 | [diff] [blame] | 264 | static const struct pci_driver northbridge_driver __pci_driver = { |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 265 | .ops = &northbridge_operations, |
Li-Ta Lo | 05c0869 | 2006-04-20 21:26:01 +0000 | [diff] [blame] | 266 | .vendor = PCI_VENDOR_ID_NS, |
| 267 | .device = PCI_DEVICE_ID_NS_GX2, |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 268 | }; |
| 269 | |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 270 | #include <cbmem.h> |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 271 | |
| 272 | static void pci_domain_set_resources(device_t dev) |
| 273 | { |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 274 | int idx; |
| 275 | u32 tomk; |
| 276 | device_t mc_dev; |
| 277 | |
| 278 | printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); |
| 279 | |
| 280 | mc_dev = dev->link_list->children; |
| 281 | if (mc_dev) { |
| 282 | tomk = get_systop() / 1024; |
| 283 | /* Report the memory regions |
| 284 | All memory up to systop except 0xa0000-0xbffff */ |
| 285 | idx = 10; |
| 286 | ram_resource(dev, idx++, 0, 640); |
| 287 | ram_resource(dev, idx++, 768, tomk - 768); /* Systop - 0xc0000 -> KB */ |
| 288 | |
Kyösti Mälkki | 42f4651 | 2013-06-27 08:20:09 +0300 | [diff] [blame] | 289 | set_top_of_ram(tomk * 1024); |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 290 | } |
| 291 | |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 292 | assign_resources(dev->link_list); |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 293 | } |
| 294 | |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 295 | static void pci_domain_enable(device_t dev) |
| 296 | { |
| 297 | printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); |
| 298 | |
| 299 | /* do this here for now -- this chip really breaks our device model */ |
| 300 | northbridge_init_early(); |
| 301 | cpubug(); |
| 302 | chipsetinit(); |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 303 | print_conf(); |
| 304 | do_vsmbios(); |
| 305 | graphics_init(); |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 306 | } |
| 307 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 308 | static struct device_operations pci_domain_ops = { |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 309 | .read_resources = pci_domain_read_resources, |
| 310 | .set_resources = pci_domain_set_resources, |
| 311 | .enable_resources = NULL, |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 312 | .scan_bus = pci_domain_scan_bus, |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 313 | .enable = pci_domain_enable, |
Kyösti Mälkki | 33e5df3 | 2013-07-03 10:51:34 +0300 | [diff] [blame] | 314 | .ops_pci_bus = pci_bus_default_ops, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 315 | }; |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 316 | |
| 317 | static void cpu_bus_init(device_t dev) |
| 318 | { |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 319 | printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); |
| 320 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 321 | initialize_cpus(dev->link_list); |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 322 | } |
| 323 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 324 | static struct device_operations cpu_bus_ops = { |
Edward O'Callaghan | 812d2a4 | 2014-10-31 08:17:23 +1100 | [diff] [blame] | 325 | .read_resources = DEVICE_NOOP, |
| 326 | .set_resources = DEVICE_NOOP, |
| 327 | .enable_resources = DEVICE_NOOP, |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 328 | .init = cpu_bus_init, |
| 329 | .scan_bus = 0, |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 330 | }; |
| 331 | |
| 332 | static void enable_dev(struct device *dev) |
| 333 | { |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 334 | printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n", |
| 335 | __func__, dev->path.type); |
Stefan Reinauer | ba09695 | 2010-04-22 09:22:15 +0000 | [diff] [blame] | 336 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 337 | /* Set the operations if it is a special bus type */ |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 338 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 339 | dev->ops = &pci_domain_ops; |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 340 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 341 | dev->ops = &cpu_bus_ops; |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 342 | } |
| 343 | |
| 344 | struct chip_operations northbridge_amd_gx2_ops = { |
Uwe Hermann | a7aa29b | 2006-11-05 18:50:49 +0000 | [diff] [blame] | 345 | CHIP_NAME("AMD GX (previously GX2) Northbridge") |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 346 | .enable_dev = enable_dev, |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 347 | }; |