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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / src / mainboard / thomson / ip1000 / gpio.c
blob: 8a03f73d6fb5556f7a656f2efe95cfda4826ef02 [file] [log] [blame]
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]15 */
16
17#define PME_DEV PNP_DEV(0x2e, 0x0a)
18#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
19#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
20
21/* Early mainboard specific GPIO setup. */
22static void mb_gpio_init(void)
23{
24 device_t dev;
25 uint16_t port;
26 uint32_t set_gpio;
27
28 /* Southbridge GPIOs. */
29 /* Set the LPC device statically. */
30 dev = PCI_DEV(0x0, 0x1f, 0x0);
31
32 /* Set the value for GPIO base address register and enable GPIO. */
Stefan Reinauer138be832010-02-27 01:50:21 +0000[diff] [blame]33 pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1));
34 pci_write_config8(dev, GPIO_CNTL, 0x10);
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]35
36 /* Set GPIO23 to high, this enables the LAN controller. */
37 udelay(10);
38 set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
39 set_gpio |= 1 << 23;
40 outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
41
Joseph Smith06025df2009-05-08 00:19:13 +0000[diff] [blame]42 /* Disable AC97 Modem */
43 pci_write_config8(dev, 0xf2, 0x40);
44
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]45 /* Super I/O GPIOs. */
46 dev = PME_DEV;
47 port = dev >> 8;
48
49 /* Enter the configuration state. */
50 outb(0x55, port);
51 pnp_set_logical_device(dev);
52 pnp_set_enable(dev, 0);
53 pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
54 pnp_set_enable(dev, 1);
55
56 /* GP21 - LED_RED */
57 outl(0x01, PME_IO_BASE_ADDR + 0x2c);
58
59 /* GP30 - FAN2_TACH */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]60 outl(0x05, PME_IO_BASE_ADDR + 0x33);
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]61
62 /* GP31 - FAN1_TACH */
63 outl(0x05, PME_IO_BASE_ADDR + 0x34);
64
65 /* GP32 - FAN2_CTRL */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]66 outl(0x04, PME_IO_BASE_ADDR + 0x35);
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]67
68 /* GP33 - FAN1_CTRL */
69 outl(0x04, PME_IO_BASE_ADDR + 0x36);
70
71 /* GP34 - AUD_MUTE_OUT_R */
72 outl(0x00, PME_IO_BASE_ADDR + 0x37);
73
74 /* GP36 - KBRST */
75 outl(0x00, PME_IO_BASE_ADDR + 0x39);
76
77 /* GP37 - A20GATE */
78 outl(0x00, PME_IO_BASE_ADDR + 0x3a);
79
80 /* GP42 - GPIO_PME_OUT */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]81 outl(0x00, PME_IO_BASE_ADDR + 0x3d);
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]82
83 /* GP50 - SER2_RI */
84 outl(0x05, PME_IO_BASE_ADDR + 0x3f);
85
86 /* GP51 - SER2_DCD */
87 outl(0x05, PME_IO_BASE_ADDR + 0x40);
88
89 /* GP52 - SER2_RX */
90 outl(0x05, PME_IO_BASE_ADDR + 0x41);
91
92 /* GP53 - SER2_TX */
93 outl(0x04, PME_IO_BASE_ADDR + 0x42);
94
95 /* GP55 - SER2_RTS */
96 outl(0x04, PME_IO_BASE_ADDR + 0x44);
97
98 /* GP56 - SER2_CTS */
99 outl(0x05, PME_IO_BASE_ADDR + 0x45);
100
101 /* GP57 - SER2_DTR */
102 outl(0x04, PME_IO_BASE_ADDR + 0x46);
103
104 /* GP60 - LED_GREEN */
105 outl(0x01, PME_IO_BASE_ADDR + 0x47);
106
107 /* GP61 - LED_YELLOW */
108 outl(0x01, PME_IO_BASE_ADDR + 0x48);
109
110 /* GP3 */
111 outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
112
113 /* GP4 */
114 outl(0x04, PME_IO_BASE_ADDR + 0x4e);
115
116 /* FAN1 */
117 outl(0x01, PME_IO_BASE_ADDR + 0x56);
118
119 /* FAN2 */
120 outl(0x01, PME_IO_BASE_ADDR + 0x57);
121
122 /* Fan Control */
123 outl(0x50, PME_IO_BASE_ADDR + 0x58);
124
125 /* Fan1 Tachometer */
126 outl(0xff, PME_IO_BASE_ADDR + 0x59);
127
128 /* Fan2 Tachometer */
129 outl(0xff, PME_IO_BASE_ADDR + 0x5a);
130
131 /* LED1 */
132 outl(0x00, PME_IO_BASE_ADDR + 0x5d);
133
134 /* LED2 */
135 outl(0x00, PME_IO_BASE_ADDR + 0x5e);
136
137 /* Keyboard Scan Code */
138 outl(0x00, PME_IO_BASE_ADDR + 0x5f);
139
140 /* Exit the configuration state. */
141 outb(0xaa, port);
142}