Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 16 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 17 | #include <string.h> |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 18 | #include <device/pci_def.h> |
| 19 | #include <arch/io.h> |
| 20 | #include <device/pnp_def.h> |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 21 | #include <cpu/x86/lapic.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 22 | #include <pc80/mc146818rtc.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 23 | #include <console/console.h> |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 24 | #include <cpu/amd/model_fxx_rev.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 25 | #include <northbridge/amd/amdk8/raminit.h> |
Edward O'Callaghan | ebe3a7a | 2015-01-05 00:27:54 +1100 | [diff] [blame] | 26 | #include <delay.h> |
Patrick Georgi | 9bd9a90 | 2010-11-20 10:31:00 +0000 | [diff] [blame] | 27 | #include <spd.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 28 | #include <cpu/x86/lapic.h> |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 29 | #include "northbridge/amd/amdk8/reset_test.c" |
| 30 | #include "northbridge/amd/amdk8/debug.c" |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 31 | #include <superio/ite/common/ite.h> |
| 32 | #include <superio/ite/it8712f/it8712f.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 33 | #include <cpu/x86/bist.h> |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 34 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 35 | #include "southbridge/amd/rs690/early_setup.c" |
| 36 | #include "southbridge/amd/sb600/early_setup.c" |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 37 | |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 38 | #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) |
Edward O'Callaghan | 76d8fd6 | 2014-05-14 19:15:08 +1000 | [diff] [blame] | 39 | #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 40 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 41 | static void memreset(int controllers, const struct mem_controller *ctrl) { } |
| 42 | static void activate_spd_rom(const struct mem_controller *ctrl) { } |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 43 | |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 44 | static inline int spd_read_byte(u32 device, u32 address) |
| 45 | { |
| 46 | return smbus_read_byte(device, address); |
| 47 | } |
| 48 | |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 49 | #include <northbridge/amd/amdk8/amdk8.h> |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 50 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
Myles Watson | 1725703 | 2009-06-04 20:18:42 +0000 | [diff] [blame] | 51 | #include "northbridge/amd/amdk8/raminit_f.c" |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 52 | #include "northbridge/amd/amdk8/coherent_ht.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 53 | #include "lib/generic_sdram.c" |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 54 | #include "resourcemap.c" |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 55 | #include "cpu/amd/dualcore/dualcore.c" |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 56 | #include "cpu/amd/model_fxx/init_cpus.c" |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 57 | #include "cpu/amd/model_fxx/fidvid.c" |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 58 | #include "northbridge/amd/amdk8/early_ht.c" |
| 59 | |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 60 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 61 | { |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 62 | static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; |
| 63 | int needs_reset = 0; |
| 64 | u32 bsp_apicid = 0; |
| 65 | msr_t msr; |
| 66 | struct cpuid_result cpuid1; |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 67 | struct sys_info *sysinfo = &sysinfo_car; |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 68 | |
Patrick Georgi | 2bd9100 | 2010-03-18 16:46:50 +0000 | [diff] [blame] | 69 | if (!cpu_init_detectedx && boot_cpu()) { |
Patrick Georgi | 776b85b | 2010-03-18 16:18:58 +0000 | [diff] [blame] | 70 | /* Nothing special needs to be done to find bus 0 */ |
| 71 | /* Allow the HT devices to be found */ |
| 72 | enumerate_ht_chain(); |
Patrick Georgi | 776b85b | 2010-03-18 16:18:58 +0000 | [diff] [blame] | 73 | /* sb600_lpc_port80(); */ |
| 74 | sb600_pci_port80(); |
| 75 | } |
| 76 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 77 | if (bist == 0) |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 78 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 79 | |
| 80 | enable_rs690_dev8(); |
| 81 | sb600_lpc_init(); |
| 82 | |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 83 | ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Edward O'Callaghan | 76d8fd6 | 2014-05-14 19:15:08 +1000 | [diff] [blame] | 84 | ite_kill_watchdog(GPIO_DEV); |
Uwe Hermann | b015d02 | 2010-09-24 18:18:20 +0000 | [diff] [blame] | 85 | |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 86 | console_init(); |
| 87 | |
| 88 | /* Halt if there was a built in self test failure */ |
| 89 | report_bist_failure(bist); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 90 | printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid); |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 91 | |
| 92 | setup_tim8690_resource_map(); |
| 93 | |
| 94 | setup_coherent_ht_domain(); |
| 95 | |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 96 | #if CONFIG_LOGICAL_CPUS |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 97 | /* It is said that we should start core1 after all core0 launched */ |
| 98 | wait_all_core0_started(); |
| 99 | start_other_cores(); |
| 100 | #endif |
| 101 | wait_all_aps_started(bsp_apicid); |
| 102 | |
| 103 | ht_setup_chains_x(sysinfo); |
| 104 | |
| 105 | /* run _early_setup before soft-reset. */ |
| 106 | rs690_early_setup(); |
| 107 | sb600_early_setup(); |
| 108 | |
| 109 | /* Check to see if processor is capable of changing FIDVID */ |
| 110 | /* otherwise it will throw a GP# when reading FIDVID_STATUS */ |
| 111 | cpuid1 = cpuid(0x80000007); |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 112 | if ((cpuid1.edx & 0x6) == 0x6 ) { |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 113 | /* Read FIDVID_STATUS */ |
| 114 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 115 | printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 116 | |
| 117 | enable_fid_change(); |
| 118 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 119 | init_fidvid_bsp(bsp_apicid); |
| 120 | |
| 121 | /* show final fid and vid */ |
| 122 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 123 | printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 124 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 125 | printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 126 | } |
| 127 | |
| 128 | needs_reset = optimize_link_coherent_ht(); |
| 129 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 130 | rs690_htinit(); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 131 | printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 132 | |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 133 | if (needs_reset) { |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 134 | printk(BIOS_INFO, "ht reset -\n"); |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 135 | soft_reset(); |
| 136 | } |
| 137 | |
| 138 | allow_all_aps_stop(bsp_apicid); |
| 139 | |
| 140 | /* It's the time to set ctrl now; */ |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 141 | printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n", |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 142 | sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 143 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 144 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 145 | |
| 146 | rs690_before_pci_init(); |
| 147 | sb600_before_pci_init(); |
| 148 | |
| 149 | post_cache_as_ram(); |
| 150 | } |