Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #define ASSEMBLY 1 |
| 21 | #define __ROMCC__ |
| 22 | |
| 23 | #define RAMINIT_SYSINFO 1 |
| 24 | #define K8_SET_FIDVID 1 |
| 25 | #define QRANK_DIMM_SUPPORT 1 |
| 26 | #if CONFIG_LOGICAL_CPUS==1 |
| 27 | #define SET_NB_CFG_54 1 |
| 28 | #endif |
| 29 | |
| 30 | #define RC0 (6<<8) |
| 31 | #define RC1 (7<<8) |
| 32 | |
| 33 | #define DIMM0 0x50 |
| 34 | #define DIMM1 0x51 |
| 35 | |
| 36 | #define ICS951462_ADDRESS 0x69 |
| 37 | #define SMBUS_HUB 0x71 |
| 38 | |
| 39 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 40 | #include <string.h> |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 41 | #include <device/pci_def.h> |
| 42 | #include <arch/io.h> |
| 43 | #include <device/pnp_def.h> |
| 44 | #include <arch/romcc_io.h> |
| 45 | #include <cpu/x86/lapic.h> |
| 46 | #include "option_table.h" |
| 47 | #include "pc80/mc146818rtc_early.c" |
| 48 | #include "pc80/serial.c" |
| 49 | #include "arch/i386/lib/console.c" |
| 50 | |
| 51 | #define post_code(x) outb(x, 0x80) |
| 52 | |
| 53 | #include <cpu/amd/model_fxx_rev.h> |
| 54 | #include "northbridge/amd/amdk8/raminit.h" |
| 55 | #include "cpu/amd/model_fxx/apic_timer.c" |
| 56 | #include "lib/delay.c" |
| 57 | |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 58 | #include "cpu/x86/lapic/boot_cpu.c" |
| 59 | #include "northbridge/amd/amdk8/reset_test.c" |
| 60 | #include "northbridge/amd/amdk8/debug.c" |
| 61 | #include "superio/ite/it8712f/it8712f_early_serial.c" |
| 62 | |
| 63 | #include "cpu/amd/mtrr/amd_earlymtrr.c" |
| 64 | #include "cpu/x86/bist.h" |
| 65 | |
| 66 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
| 67 | |
| 68 | #include "southbridge/amd/rs690/rs690_early_setup.c" |
| 69 | #include "southbridge/amd/sb600/sb600_early_setup.c" |
| 70 | |
| 71 | /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ |
| 72 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 73 | { |
| 74 | } |
| 75 | |
| 76 | /* called in raminit_f.c */ |
| 77 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 78 | { |
| 79 | } |
| 80 | |
| 81 | /*called in raminit_f.c */ |
| 82 | static inline int spd_read_byte(u32 device, u32 address) |
| 83 | { |
| 84 | return smbus_read_byte(device, address); |
| 85 | } |
| 86 | |
| 87 | #include "northbridge/amd/amdk8/amdk8.h" |
| 88 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
Myles Watson | 1725703 | 2009-06-04 20:18:42 +0000 | [diff] [blame] | 89 | #include "northbridge/amd/amdk8/raminit_f.c" |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 90 | #include "northbridge/amd/amdk8/coherent_ht.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame^] | 91 | #include "lib/generic_sdram.c" |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 92 | #include "resourcemap.c" |
| 93 | |
| 94 | #include "cpu/amd/dualcore/dualcore.c" |
| 95 | |
| 96 | #include "cpu/amd/car/copy_and_run.c" |
| 97 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 98 | |
| 99 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 100 | |
| 101 | #include "cpu/amd/model_fxx/fidvid.c" |
| 102 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 103 | #if CONFIG_USE_FALLBACK_IMAGE == 1 |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 104 | |
| 105 | #include "northbridge/amd/amdk8/early_ht.c" |
| 106 | |
| 107 | void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) |
| 108 | { |
| 109 | /* Is this a cpu only reset? Is this a secondary cpu? */ |
| 110 | if ((cpu_init_detectedx) || (!boot_cpu())) { |
| 111 | if (last_boot_normal()) { /* RTC already inited */ |
| 112 | goto normal_image; |
| 113 | } else { |
| 114 | goto fallback_image; |
| 115 | } |
| 116 | } |
| 117 | /* Nothing special needs to be done to find bus 0 */ |
| 118 | /* Allow the HT devices to be found */ |
| 119 | enumerate_ht_chain(); |
| 120 | |
| 121 | /* sb600_lpc_port80(); */ |
| 122 | sb600_pci_port80(); |
| 123 | |
| 124 | /* Is this a deliberate reset by the bios */ |
| 125 | if (bios_reset_detected() && last_boot_normal()) { |
| 126 | goto normal_image; |
| 127 | } |
| 128 | /* This is the primary cpu how should I boot? */ |
| 129 | else if (do_normal_boot()) { |
| 130 | goto normal_image; |
| 131 | } else { |
| 132 | goto fallback_image; |
| 133 | } |
| 134 | normal_image: |
| 135 | post_code(0x23); |
| 136 | __asm__ volatile ("jmp __normal_image": /* outputs */ |
| 137 | :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); |
| 138 | |
| 139 | fallback_image: |
| 140 | post_code(0x25); |
| 141 | } |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 142 | #endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 143 | |
| 144 | void real_main(unsigned long bist, unsigned long cpu_init_detectedx); |
| 145 | |
| 146 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 147 | { |
| 148 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 149 | #if CONFIG_USE_FALLBACK_IMAGE == 1 |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 150 | failover_process(bist, cpu_init_detectedx); |
| 151 | #endif |
| 152 | real_main(bist, cpu_init_detectedx); |
| 153 | } |
| 154 | |
| 155 | void real_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 156 | { |
| 157 | static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; |
| 158 | int needs_reset = 0; |
| 159 | u32 bsp_apicid = 0; |
| 160 | msr_t msr; |
| 161 | struct cpuid_result cpuid1; |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 162 | struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 163 | |
| 164 | |
| 165 | if (bist == 0) { |
| 166 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 167 | } |
| 168 | |
| 169 | enable_rs690_dev8(); |
| 170 | sb600_lpc_init(); |
| 171 | |
| 172 | /* it8712f_enable_serial does not use its 1st parameter. */ |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 173 | it8712f_enable_serial(0, CONFIG_TTYS0_BASE); |
Daniel Toussaint | da6d92b | 2009-04-06 13:38:54 +0000 | [diff] [blame] | 174 | it8712f_kill_watchdog(); |
| 175 | uart_init(); |
| 176 | console_init(); |
| 177 | |
| 178 | /* Halt if there was a built in self test failure */ |
| 179 | report_bist_failure(bist); |
| 180 | printk_debug("bsp_apicid=0x%x\n", bsp_apicid); |
| 181 | |
| 182 | setup_tim8690_resource_map(); |
| 183 | |
| 184 | setup_coherent_ht_domain(); |
| 185 | |
| 186 | #if CONFIG_LOGICAL_CPUS==1 |
| 187 | /* It is said that we should start core1 after all core0 launched */ |
| 188 | wait_all_core0_started(); |
| 189 | start_other_cores(); |
| 190 | #endif |
| 191 | wait_all_aps_started(bsp_apicid); |
| 192 | |
| 193 | ht_setup_chains_x(sysinfo); |
| 194 | |
| 195 | /* run _early_setup before soft-reset. */ |
| 196 | rs690_early_setup(); |
| 197 | sb600_early_setup(); |
| 198 | |
| 199 | /* Check to see if processor is capable of changing FIDVID */ |
| 200 | /* otherwise it will throw a GP# when reading FIDVID_STATUS */ |
| 201 | cpuid1 = cpuid(0x80000007); |
| 202 | if( (cpuid1.edx & 0x6) == 0x6 ) { |
| 203 | |
| 204 | /* Read FIDVID_STATUS */ |
| 205 | msr=rdmsr(0xc0010042); |
| 206 | printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); |
| 207 | |
| 208 | enable_fid_change(); |
| 209 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 210 | init_fidvid_bsp(bsp_apicid); |
| 211 | |
| 212 | /* show final fid and vid */ |
| 213 | msr=rdmsr(0xc0010042); |
| 214 | printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); |
| 215 | |
| 216 | } else { |
| 217 | printk_debug("Changing FIDVID not supported\n"); |
| 218 | } |
| 219 | |
| 220 | needs_reset = optimize_link_coherent_ht(); |
| 221 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 222 | rs690_htinit(); |
| 223 | printk_debug("needs_reset=0x%x\n", needs_reset); |
| 224 | |
| 225 | |
| 226 | if (needs_reset) { |
| 227 | print_info("ht reset -\r\n"); |
| 228 | soft_reset(); |
| 229 | } |
| 230 | |
| 231 | allow_all_aps_stop(bsp_apicid); |
| 232 | |
| 233 | /* It's the time to set ctrl now; */ |
| 234 | printk_debug("sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n", |
| 235 | sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 236 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 237 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 238 | |
| 239 | rs690_before_pci_init(); |
| 240 | sb600_before_pci_init(); |
| 241 | |
| 242 | post_cache_as_ram(); |
| 243 | } |