Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2010 Siemens AG, Inc. |
| 6 | * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 16 | */ |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 17 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 18 | #include <stdint.h> |
| 19 | #include <string.h> |
| 20 | #include <device/pci_def.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <device/pnp_def.h> |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 23 | #include <cpu/x86/lapic.h> |
| 24 | #include <pc80/mc146818rtc.h> |
| 25 | #include <console/console.h> |
Patrick Georgi | f771e56 | 2014-05-03 09:12:55 +0200 | [diff] [blame] | 26 | #include <spd.h> |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 27 | |
| 28 | #include <cpu/amd/model_fxx_rev.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 29 | #include <northbridge/amd/amdk8/raminit.h> |
Edward O'Callaghan | ebe3a7a | 2015-01-05 00:27:54 +1100 | [diff] [blame] | 30 | #include <delay.h> |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 31 | |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 32 | #include <cpu/x86/lapic.h> |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 33 | #include "northbridge/amd/amdk8/reset_test.c" |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 34 | #include <superio/ite/common/ite.h> |
| 35 | #include <superio/ite/it8712f/it8712f.h> |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 36 | |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 37 | #include <cpu/x86/bist.h> |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 38 | |
| 39 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
| 40 | |
| 41 | #include "southbridge/amd/rs690/early_setup.c" |
| 42 | #include "southbridge/amd/sb600/early_setup.c" |
| 43 | #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ |
| 44 | |
Dennis Wassenberg | 498c32a | 2014-10-14 17:29:36 +0200 | [diff] [blame] | 45 | #define SERIAL_DEV PNP_DEV(0x2e, CONFIG_UART_FOR_CONSOLE == 1 ? IT8712F_SP2 : IT8712F_SP1) |
Edward O'Callaghan | 76d8fd6 | 2014-05-14 19:15:08 +1000 | [diff] [blame] | 46 | #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 47 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 48 | /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ |
| 49 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 50 | { |
| 51 | } |
| 52 | |
| 53 | /* called in raminit_f.c */ |
| 54 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 55 | { |
| 56 | } |
| 57 | |
| 58 | /*called in raminit_f.c */ |
| 59 | static inline int spd_read_byte(u32 device, u32 address) |
| 60 | { |
| 61 | return smbus_read_byte(device, address); |
| 62 | } |
| 63 | |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 64 | #include <northbridge/amd/amdk8/amdk8.h> |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 65 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
| 66 | #include "northbridge/amd/amdk8/raminit_f.c" |
| 67 | #include "northbridge/amd/amdk8/coherent_ht.c" |
| 68 | #include "lib/generic_sdram.c" |
| 69 | #include "resourcemap.c" |
| 70 | #include "cpu/amd/dualcore/dualcore.c" |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 71 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 72 | #include "cpu/amd/model_fxx/fidvid.c" |
| 73 | #include "northbridge/amd/amdk8/early_ht.c" |
| 74 | |
| 75 | #define __WARNING__(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg) |
| 76 | #define __DEBUG__(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg) |
| 77 | #define __INFO__(fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg) |
| 78 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 79 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 80 | { |
| 81 | static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; |
| 82 | int needs_reset = 0; |
| 83 | u32 bsp_apicid = 0; |
| 84 | msr_t msr; |
| 85 | struct cpuid_result cpuid1; |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 86 | struct sys_info *sysinfo = &sysinfo_car; |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 87 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 88 | if (!cpu_init_detectedx && boot_cpu()) { |
| 89 | /* Nothing special needs to be done to find bus 0 */ |
| 90 | /* Allow the HT devices to be found */ |
| 91 | enumerate_ht_chain(); |
| 92 | |
| 93 | /* sb600_lpc_port80(); */ |
| 94 | sb600_pci_port80(); |
| 95 | } |
| 96 | |
| 97 | if (bist == 0) { |
| 98 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 99 | } |
| 100 | |
| 101 | enable_rs690_dev8(); // enable CFG access to Dev8, which is the SB P2P Bridge |
| 102 | sb600_lpc_init(); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 103 | #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0) |
| 104 | check_cmos(); // rebooting in case of corrupted cmos !!!!! |
| 105 | #endif |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 106 | ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Edward O'Callaghan | 76d8fd6 | 2014-05-14 19:15:08 +1000 | [diff] [blame] | 107 | ite_kill_watchdog(GPIO_DEV); |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 108 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 109 | console_init(); |
| 110 | #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 1) |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 111 | check_cmos(); // rebooting in case of corrupted cmos !!!!! |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 112 | #endif |
| 113 | post_code(0x03); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 114 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 115 | /* Halt if there was a built in self test failure */ |
| 116 | report_bist_failure(bist); |
| 117 | __DEBUG__("bsp_apicid=0x%x\n", bsp_apicid); |
| 118 | |
| 119 | setup_sitemp_resource_map(); |
| 120 | |
| 121 | setup_coherent_ht_domain(); |
| 122 | |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 123 | #if CONFIG_LOGICAL_CPUS |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 124 | /* It is said that we should start core1 after all core0 launched */ |
| 125 | wait_all_core0_started(); |
| 126 | start_other_cores(); |
| 127 | #endif |
| 128 | wait_all_aps_started(bsp_apicid); |
| 129 | |
| 130 | ht_setup_chains_x(sysinfo); |
| 131 | |
| 132 | /* run _early_setup before soft-reset. */ |
| 133 | rs690_early_setup(); |
| 134 | sb600_early_setup(); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 135 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 136 | post_code(0x04); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 137 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 138 | /* Check to see if processor is capable of changing FIDVID */ |
| 139 | /* otherwise it will throw a GP# when reading FIDVID_STATUS */ |
| 140 | cpuid1 = cpuid(0x80000007); |
| 141 | if( (cpuid1.edx & 0x6) == 0x6 ) { |
| 142 | |
| 143 | /* Read FIDVID_STATUS */ |
| 144 | msr=rdmsr(0xc0010042); |
| 145 | __DEBUG__("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); |
| 146 | |
| 147 | enable_fid_change(); |
| 148 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 149 | init_fidvid_bsp(bsp_apicid); |
| 150 | |
| 151 | /* show final fid and vid */ |
| 152 | msr=rdmsr(0xc0010042); |
| 153 | __DEBUG__("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); |
| 154 | |
| 155 | } else { |
| 156 | __DEBUG__("Changing FIDVID not supported\n"); |
| 157 | } |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 158 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 159 | post_code(0x05); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 160 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 161 | needs_reset = optimize_link_coherent_ht(); |
| 162 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 163 | rs690_htinit(); |
| 164 | __DEBUG__("needs_reset=0x%x\n", needs_reset); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 165 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 166 | post_code(0x06); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 167 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 168 | if (needs_reset) { |
| 169 | __INFO__("ht reset -\n"); |
| 170 | soft_reset(); |
| 171 | } |
| 172 | |
| 173 | allow_all_aps_stop(bsp_apicid); |
| 174 | |
| 175 | /* It's the time to set ctrl now; */ |
| 176 | __DEBUG__("sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n", |
| 177 | sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 178 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 179 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 180 | post_code(0x07); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 181 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 182 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 183 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 184 | post_code(0x08); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 185 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 186 | rs690_before_pci_init(); // does nothing |
| 187 | sb600_before_pci_init(); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 188 | |
Josef Kellermann | bfa7ee5 | 2011-05-11 07:47:43 +0000 | [diff] [blame] | 189 | post_cache_as_ram(); |
| 190 | } |