Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 3 | * |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | // __PRE_RAM__ means: use "unsigned" for device, not a struct. |
Stefan Reinauer | 5e32823 | 2010-03-29 19:19:16 +0000 | [diff] [blame] | 18 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 19 | #include <stdint.h> |
| 20 | #include <string.h> |
| 21 | #include <arch/io.h> |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 22 | #include <device/pci_def.h> |
| 23 | #include <device/pnp_def.h> |
| 24 | #include <cpu/x86/lapic.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 25 | #include <lib.h> |
Kyösti Mälkki | 12d681b | 2014-06-14 18:51:34 +0300 | [diff] [blame] | 26 | #include <arch/acpi.h> |
Kyösti Mälkki | a7c9611 | 2013-10-13 20:41:57 +0300 | [diff] [blame] | 27 | #include <cbmem.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 28 | #include <pc80/mc146818rtc.h> |
Stefan Reinauer | 8a7d34b | 2010-02-22 09:15:13 +0000 | [diff] [blame] | 29 | #include <console/console.h> |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 30 | #include <cpu/x86/bist.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 31 | #include <halt.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 32 | #include <northbridge/intel/i945/i945.h> |
| 33 | #include <northbridge/intel/i945/raminit.h> |
| 34 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 35 | #include "option_table.h" |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 36 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 37 | void setup_ich7_gpios(void) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 38 | { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 39 | printk(BIOS_DEBUG, " GPIOS..."); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 40 | /* General Registers */ |
| 41 | outl(0xbfc0f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ |
| 42 | outl(0x70a87d83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ |
Patrick Georgi | ef32965 | 2011-01-14 07:41:42 +0000 | [diff] [blame] | 43 | // ------------------------------------------------------------ |
| 44 | // 0 - GPO6 - Enable power of SATA channel 0 |
| 45 | // 0 - GPO9 - Wireless LAN power on |
| 46 | // 0 - GPO15 - FAN on |
| 47 | // 1 - GPO22 - FWH WP |
| 48 | // 1 - GPO24 - GPS on |
| 49 | // 0 - GPO25 - External Antenna Mux on |
| 50 | // 0 - GPO26 - BT on |
| 51 | // 0 - GPO27 - GSM on |
| 52 | outl(0x01400000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 53 | // ------------------------------------------------------------ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 54 | /* Output Control Registers */ |
| 55 | outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ |
| 56 | /* Input Control Registers */ |
| 57 | outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ |
| 58 | outl(0x000100e8, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ |
| 59 | outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ |
Patrick Georgi | ef32965 | 2011-01-14 07:41:42 +0000 | [diff] [blame] | 60 | // ------------------------------------------------------------ |
| 61 | // 1 - GPO48 - FWH TBL# |
| 62 | outl(0x00010000, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ |
| 63 | // ------------------------------------------------------------ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 64 | } |
| 65 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 66 | static void ich7_enable_lpc(void) |
| 67 | { |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 68 | int lpt_en = 0; |
Patrick Georgi | b251753 | 2011-05-10 21:53:13 +0000 | [diff] [blame] | 69 | if (read_option(lpt, 0) != 0) { |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 70 | lpt_en = 1<<2; // enable LPT |
| 71 | } |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 72 | // Enable Serial IRQ |
| 73 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); |
| 74 | // decode range |
| 75 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); |
| 76 | // decode range |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 77 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 78 | // Enable 0x02e0 |
| 79 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1); |
| 80 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c); |
| 81 | // COM3 decode |
| 82 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); |
| 83 | // COM4 decode |
| 84 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); |
| 85 | } |
| 86 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 87 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 88 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 89 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 90 | * but safe anyways" method. |
| 91 | */ |
| 92 | static inline void pnp_enter_ext_func_mode(device_t dev) |
| 93 | { |
| 94 | unsigned int port = dev >> 8; |
| 95 | outb(0x55, port); |
| 96 | } |
| 97 | |
| 98 | static void pnp_exit_ext_func_mode(device_t dev) |
| 99 | { |
| 100 | unsigned int port = dev >> 8; |
| 101 | outb(0xaa, port); |
| 102 | } |
| 103 | |
| 104 | static void pnp_write_register(device_t dev, int reg, int val) |
| 105 | { |
| 106 | unsigned int port = dev >> 8; |
| 107 | outb(reg, port); |
| 108 | outb(val, port+1); |
| 109 | } |
| 110 | |
| 111 | static void early_superio_config(void) |
| 112 | { |
| 113 | device_t dev; |
| 114 | |
| 115 | dev=PNP_DEV(0x2e, 0x00); |
| 116 | |
| 117 | pnp_enter_ext_func_mode(dev); |
| 118 | pnp_write_register(dev, 0x01, 0x94); // Extended Parport modes |
| 119 | pnp_write_register(dev, 0x02, 0x88); // UART power on |
| 120 | pnp_write_register(dev, 0x03, 0x72); // Floppy |
| 121 | pnp_write_register(dev, 0x04, 0x01); // EPP + SPP |
| 122 | pnp_write_register(dev, 0x14, 0x03); // Floppy |
| 123 | pnp_write_register(dev, 0x20, (0x3f0 >> 2)); // Floppy |
| 124 | pnp_write_register(dev, 0x23, (0x378 >> 2)); // PP base |
| 125 | pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base |
| 126 | pnp_write_register(dev, 0x25, (0x2f8 >> 2)); // UART2 base |
| 127 | pnp_write_register(dev, 0x26, (2 << 4) | 0); // FDC + PP DMA |
| 128 | pnp_write_register(dev, 0x27, (6 << 4) | 7); // FDC + PP DMA |
| 129 | pnp_write_register(dev, 0x28, (4 << 4) | 3); // UART1,2 IRQ |
| 130 | /* These are the SMI status registers in the SIO: */ |
| 131 | pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base |
| 132 | |
| 133 | pnp_write_register(dev, 0x31, 0x00); // GPIO1 DIR |
| 134 | pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL |
| 135 | pnp_write_register(dev, 0x33, 0x40); // GPIO2 DIR |
| 136 | pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL |
| 137 | pnp_write_register(dev, 0x35, 0xff); // GPIO3 DIR |
| 138 | pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL |
| 139 | pnp_write_register(dev, 0x37, 0xe0); // GPIO4 DIR |
| 140 | pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL |
| 141 | pnp_write_register(dev, 0x39, 0x80); // GPIO4 POL |
| 142 | |
| 143 | pnp_exit_ext_func_mode(dev); |
| 144 | } |
| 145 | |
| 146 | static void rcba_config(void) |
| 147 | { |
| 148 | /* Set up virtual channel 0 */ |
| 149 | //RCBA32(0x0014) = 0x80000001; |
| 150 | //RCBA32(0x001c) = 0x03128010; |
| 151 | |
| 152 | /* Device 1f interrupt pin register */ |
| 153 | RCBA32(0x3100) = 0x00042220; |
| 154 | /* Device 1d interrupt pin register */ |
| 155 | RCBA32(0x310c) = 0x00214321; |
| 156 | |
| 157 | /* dev irq route register */ |
| 158 | RCBA16(0x3140) = 0x0232; |
| 159 | RCBA16(0x3142) = 0x3246; |
| 160 | RCBA16(0x3144) = 0x0237; |
| 161 | RCBA16(0x3146) = 0x3201; |
| 162 | RCBA16(0x3148) = 0x3216; |
| 163 | |
| 164 | /* Enable IOAPIC */ |
| 165 | RCBA8(0x31ff) = 0x03; |
| 166 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 167 | /* Disable unused devices */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 168 | RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 169 | FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA; |
| 170 | RCBA32(0x3418) |= (1 << 0); // Required. |
| 171 | |
| 172 | /* Enable PCIe Root Port Clock Gate */ |
| 173 | // RCBA32(0x341c) = 0x00000001; |
| 174 | |
| 175 | /* This should probably go into the ACPI OS Init trap */ |
| 176 | |
| 177 | /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ |
| 178 | RCBA32(0x1e84) = 0x00020001; |
| 179 | RCBA32(0x1e80) = 0x0000fe01; |
| 180 | |
| 181 | /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ |
| 182 | RCBA32(0x1e9c) = 0x000200f0; |
| 183 | RCBA32(0x1e98) = 0x000c0801; |
| 184 | } |
| 185 | |
| 186 | static void early_ich7_init(void) |
| 187 | { |
| 188 | uint8_t reg8; |
| 189 | uint32_t reg32; |
| 190 | |
| 191 | // program secondary mlt XXX byte? |
| 192 | pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 193 | |
| 194 | // reset rtc power status |
| 195 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 196 | reg8 &= ~(1 << 2); |
| 197 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); |
| 198 | |
| 199 | // usb transient disconnect |
| 200 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 201 | reg8 |= (3 << 0); |
| 202 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 203 | |
| 204 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 205 | reg32 |= (1 << 29) | (1 << 17); |
| 206 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 207 | |
| 208 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 209 | reg32 |= (1 << 31) | (1 << 27); |
| 210 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 211 | |
| 212 | RCBA32(0x0088) = 0x0011d000; |
| 213 | RCBA16(0x01fc) = 0x060f; |
| 214 | RCBA32(0x01f4) = 0x86000040; |
| 215 | RCBA32(0x0214) = 0x10030549; |
| 216 | RCBA32(0x0218) = 0x00020504; |
| 217 | RCBA8(0x0220) = 0xc5; |
| 218 | reg32 = RCBA32(0x3410); |
| 219 | reg32 |= (1 << 6); |
| 220 | RCBA32(0x3410) = reg32; |
| 221 | reg32 = RCBA32(0x3430); |
| 222 | reg32 &= ~(3 << 0); |
| 223 | reg32 |= (1 << 0); |
| 224 | RCBA32(0x3430) = reg32; |
| 225 | RCBA32(0x3418) |= (1 << 0); |
| 226 | RCBA16(0x0200) = 0x2008; |
| 227 | RCBA8(0x2027) = 0x0d; |
| 228 | RCBA16(0x3e08) |= (1 << 7); |
| 229 | RCBA16(0x3e48) |= (1 << 7); |
| 230 | RCBA32(0x3e0e) |= (1 << 7); |
| 231 | RCBA32(0x3e4e) |= (1 << 7); |
| 232 | |
| 233 | // next step only on ich7m b0 and later: |
| 234 | reg32 = RCBA32(0x2034); |
| 235 | reg32 &= ~(0x0f << 16); |
| 236 | reg32 |= (5 << 16); |
| 237 | RCBA32(0x2034) = reg32; |
| 238 | } |
| 239 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 240 | static void init_artec_dongle(void) |
| 241 | { |
| 242 | // Enable 4MB decoding |
| 243 | outb(0xf1, 0x88); |
| 244 | outb(0xf4, 0x88); |
| 245 | } |
| 246 | |
Aaron Durbin | a0a3727 | 2014-08-14 08:35:11 -0500 | [diff] [blame] | 247 | #include <cpu/intel/romstage.h> |
Stefan Reinauer | 3e1f524 | 2010-04-12 23:04:29 +0000 | [diff] [blame] | 248 | void main(unsigned long bist) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 249 | { |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 250 | int s3resume = 0; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 251 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 252 | if (bist == 0) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 253 | enable_lapic(); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 254 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 255 | /* Force PCIRST# */ |
| 256 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); |
Stefan Reinauer | bc8613e | 2010-08-25 18:35:42 +0000 | [diff] [blame] | 257 | udelay(200 * 1000); |
| 258 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 259 | |
Stefan Reinauer | bc8613e | 2010-08-25 18:35:42 +0000 | [diff] [blame] | 260 | ich7_enable_lpc(); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 261 | early_superio_config(); |
| 262 | |
| 263 | /* Set up the console */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 264 | console_init(); |
| 265 | |
| 266 | /* Halt if there was a built in self test failure */ |
| 267 | report_bist_failure(bist); |
| 268 | |
| 269 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 270 | printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); |
| 271 | outb(0x6, 0xcf9); |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 272 | halt(); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 273 | } |
| 274 | |
| 275 | /* Perform some early chipset initialization required |
| 276 | * before RAM initialization can work |
| 277 | */ |
| 278 | i945_early_initialization(); |
| 279 | |
| 280 | /* This has to happen after i945_early_initialization() */ |
| 281 | init_artec_dongle(); |
| 282 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 283 | s3resume = southbridge_detect_s3_resume(); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 284 | |
| 285 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 286 | enable_smbus(); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 287 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 288 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
| 289 | dump_spd_registers(); |
| 290 | #endif |
| 291 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 292 | sdram_initialize(s3resume ? 2 : 0, NULL); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 293 | |
| 294 | /* Perform some initialization that must run before stage2 */ |
| 295 | early_ich7_init(); |
| 296 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 297 | /* This should probably go away. Until now it is required |
| 298 | * and mainboard specific |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 299 | */ |
| 300 | rcba_config(); |
| 301 | |
| 302 | /* Chipset Errata! */ |
| 303 | fixup_i945_errata(); |
| 304 | |
| 305 | /* Initialize the internal PCIe links before we go into stage2 */ |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 306 | i945_late_initialization(s3resume); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 307 | } |