Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
Kyösti Mälkki | 7809356 | 2014-11-11 17:22:23 +0200 | [diff] [blame] | 5 | * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC |
| 6 | * Copyright (C) 2014 Kyösti Mälkki <kyosti.malkki@gmail.com> |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <stdint.h> |
| 19 | #include <string.h> |
| 20 | #include <device/pci_def.h> |
| 21 | #include <device/pci_ids.h> |
| 22 | #include <arch/acpi.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <arch/stages.h> |
| 25 | #include <device/pnp_def.h> |
| 26 | #include <arch/cpu.h> |
| 27 | #include <cpu/x86/lapic.h> |
| 28 | #include <console/console.h> |
Aaron Durbin | dc9f5cd | 2015-09-08 13:34:43 -0500 | [diff] [blame] | 29 | #include <commonlib/loglevel.h> |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 30 | #include <cpu/x86/mtrr.h> |
| 31 | #include <cpu/amd/car.h> |
| 32 | #include <northbridge/amd/agesa/agesawrapper.h> |
Kyösti Mälkki | 7809356 | 2014-11-11 17:22:23 +0200 | [diff] [blame] | 33 | #include <southbridge/amd/cimx/cimx_util.h> |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 34 | #include <cpu/x86/bist.h> |
| 35 | #include <cpu/x86/cache.h> |
| 36 | #include <sb_cimx.h> |
| 37 | #include "SBPLATFORM.h" |
| 38 | #include "cbmem.h" |
| 39 | #include <cpu/amd/mtrr.h> |
| 40 | #include <cpu/amd/agesa/s3_resume.h> |
Kyösti Mälkki | 8c190f3 | 2014-11-14 16:20:22 +0200 | [diff] [blame] | 41 | #include <superio/nuvoton/common/nuvoton.h> |
| 42 | #include <superio/nuvoton/nct5104d/nct5104d.h> |
Kyösti Mälkki | 7809356 | 2014-11-11 17:22:23 +0200 | [diff] [blame] | 43 | #include "gpio_ftns.h" |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 44 | |
Kyösti Mälkki | 8c190f3 | 2014-11-14 16:20:22 +0200 | [diff] [blame] | 45 | #define SIO_PORT 0x2e |
| 46 | #define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 47 | |
Kyösti Mälkki | 7809356 | 2014-11-11 17:22:23 +0200 | [diff] [blame] | 48 | static void early_lpc_init(void); |
| 49 | |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 50 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 51 | { |
| 52 | u32 val; |
| 53 | |
| 54 | /* |
| 55 | * All cores: allow caching of flash chip code and data |
| 56 | * (there are no cache-as-ram reliability concerns with family 14h) |
| 57 | */ |
| 58 | __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); |
| 59 | __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); |
| 60 | |
| 61 | /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ |
| 62 | __writemsr (0xc0010062, 0); |
| 63 | |
| 64 | amd_initmmio(); |
| 65 | |
| 66 | if (!cpu_init_detectedx && boot_cpu()) { |
| 67 | post_code(0x30); |
| 68 | sb_Poweron_Init(); |
Kyösti Mälkki | 7809356 | 2014-11-11 17:22:23 +0200 | [diff] [blame] | 69 | early_lpc_init(); |
| 70 | |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 71 | |
| 72 | post_code(0x31); |
Kyösti Mälkki | 8c190f3 | 2014-11-14 16:20:22 +0200 | [diff] [blame] | 73 | nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Kyösti Mälkki | f09e6d4 | 2015-01-10 12:13:23 +0200 | [diff] [blame] | 74 | console_init(); |
| 75 | } |
| 76 | |
| 77 | /* Halt if there was a built in self test failure */ |
| 78 | post_code(0x34); |
| 79 | report_bist_failure(bist); |
| 80 | |
| 81 | /* Load MPB */ |
| 82 | val = cpuid_eax(1); |
| 83 | printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); |
| 84 | printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); |
| 85 | |
| 86 | post_code(0x37); |
| 87 | agesawrapper_amdinitreset(); |
| 88 | |
| 89 | post_code(0x39); |
| 90 | agesawrapper_amdinitearly(); |
| 91 | |
| 92 | int s3resume = acpi_is_wakeup_s3(); |
| 93 | if (!s3resume) { |
| 94 | post_code(0x40); |
| 95 | agesawrapper_amdinitpost(); |
| 96 | |
| 97 | post_code(0x42); |
| 98 | agesawrapper_amdinitenv(); |
| 99 | amd_initenv(); |
| 100 | |
| 101 | } else { /* S3 detect */ |
| 102 | printk(BIOS_INFO, "S3 detected\n"); |
| 103 | |
| 104 | post_code(0x60); |
| 105 | agesawrapper_amdinitresume(); |
| 106 | |
| 107 | agesawrapper_amds3laterestore(); |
| 108 | |
| 109 | post_code(0x61); |
| 110 | prepare_for_resume(); |
| 111 | } |
| 112 | |
| 113 | post_code(0x50); |
| 114 | copy_and_run(); |
| 115 | printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); |
| 116 | |
| 117 | post_code(0x54); /* Should never see this post code. */ |
| 118 | } |
Kyösti Mälkki | 7809356 | 2014-11-11 17:22:23 +0200 | [diff] [blame] | 119 | |
| 120 | static void early_lpc_init(void) |
| 121 | { |
| 122 | u32 mmio_base; |
| 123 | |
| 124 | /* PC Engines requires system boot when power is applied. This feature is |
| 125 | * controlled in PM_REG 5Bh register. "Always Power On" works by writing a |
| 126 | * value of 05h. |
| 127 | */ |
| 128 | u8 bdata = pm_ioread(SB_PMIOA_REG5B); |
| 129 | bdata &= 0xf8; //clear bits 0-2 |
| 130 | bdata |= 0x05; //set bits 0,2 |
| 131 | pm_iowrite(SB_PMIOA_REG5B, bdata); |
| 132 | |
| 133 | /* Multi-function pins switch to GPIO0-35, these pins are shared with PCI pins */ |
| 134 | bdata = pm_ioread(SB_PMIOA_REGEA); |
| 135 | bdata &= 0xfe; //clear bit 0 |
| 136 | bdata |= 0x01; //set bit 0 |
| 137 | pm_iowrite(SB_PMIOA_REGEA, bdata); |
| 138 | |
| 139 | //configure required GPIOs |
| 140 | mmio_base = find_gpio_base(); |
| 141 | configure_gpio(mmio_base, GPIO_10, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); |
| 142 | configure_gpio(mmio_base, GPIO_11, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); |
| 143 | configure_gpio(mmio_base, GPIO_15, GPIO_FTN_1, GPIO_INPUT); |
| 144 | configure_gpio(mmio_base, GPIO_16, GPIO_FTN_1, GPIO_INPUT); |
| 145 | configure_gpio(mmio_base, GPIO_17, GPIO_FTN_1, GPIO_INPUT); |
| 146 | configure_gpio(mmio_base, GPIO_18, GPIO_FTN_1, GPIO_INPUT); |
| 147 | configure_gpio(mmio_base, GPIO_187, GPIO_FTN_1, GPIO_INPUT); |
| 148 | configure_gpio(mmio_base, GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); |
| 149 | configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); |
| 150 | configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); |
| 151 | } |