pcengines/apu1: Implement board GPIOs
Some GPIO pins are shared with (disabled) PCI bridge 0:14.4.
As our PCI subsystem currently does not configure PCI bridges that are
marked disabled, but remain visible in the hardware, we cannot mark 0:14.4
disabled in devicetree just yet.
Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8326
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index c555536..e9b9400 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -2,6 +2,8 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC
+ * Copyright (C) 2014 Kyösti Mälkki <kyosti.malkki@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -32,6 +34,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
+#include <southbridge/amd/cimx/cimx_util.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/cache.h>
#include <sb_cimx.h>
@@ -41,10 +44,13 @@
#include <cpu/amd/agesa/s3_resume.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct5104d/nct5104d.h>
+#include "gpio_ftns.h"
#define SIO_PORT 0x2e
#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
+static void early_lpc_init(void);
+
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
@@ -64,6 +70,8 @@
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
+ early_lpc_init();
+
post_code(0x31);
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -112,3 +120,36 @@
post_code(0x54); /* Should never see this post code. */
}
+
+static void early_lpc_init(void)
+{
+ u32 mmio_base;
+
+ /* PC Engines requires system boot when power is applied. This feature is
+ * controlled in PM_REG 5Bh register. "Always Power On" works by writing a
+ * value of 05h.
+ */
+ u8 bdata = pm_ioread(SB_PMIOA_REG5B);
+ bdata &= 0xf8; //clear bits 0-2
+ bdata |= 0x05; //set bits 0,2
+ pm_iowrite(SB_PMIOA_REG5B, bdata);
+
+ /* Multi-function pins switch to GPIO0-35, these pins are shared with PCI pins */
+ bdata = pm_ioread(SB_PMIOA_REGEA);
+ bdata &= 0xfe; //clear bit 0
+ bdata |= 0x01; //set bit 0
+ pm_iowrite(SB_PMIOA_REGEA, bdata);
+
+ //configure required GPIOs
+ mmio_base = find_gpio_base();
+ configure_gpio(mmio_base, GPIO_10, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
+ configure_gpio(mmio_base, GPIO_11, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
+ configure_gpio(mmio_base, GPIO_15, GPIO_FTN_1, GPIO_INPUT);
+ configure_gpio(mmio_base, GPIO_16, GPIO_FTN_1, GPIO_INPUT);
+ configure_gpio(mmio_base, GPIO_17, GPIO_FTN_1, GPIO_INPUT);
+ configure_gpio(mmio_base, GPIO_18, GPIO_FTN_1, GPIO_INPUT);
+ configure_gpio(mmio_base, GPIO_187, GPIO_FTN_1, GPIO_INPUT);
+ configure_gpio(mmio_base, GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
+ configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
+ configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
+}