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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / src / mainboard / google / peppy / i915io.c
blob: a97f994591e2af98e77a0854c7fa2791b8de1c36 [file] [log] [blame]
Ronald G. Minnich9518b562013-09-19 16:45:22 -0700[diff] [blame]1/*
2* This file is part of the coreboot project.
3*
4* Copyright 2013 Google Inc.
5*
6* This program is free software; you can redistribute it and/or modify
7* it under the terms of the GNU General Public License as published by
8* the Free Software Foundation; version 2 of the License.
9*
10* This program is distributed in the hope that it will be useful,
11* but WITHOUT ANY WARRANTY; without even the implied warranty of
12* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13* GNU General Public License for more details.
Ronald G. Minnich9518b562013-09-19 16:45:22 -0700[diff] [blame]14*/
15
16#include <stdint.h>
17#include <console/console.h>
18#include <delay.h>
19#include <drivers/intel/gma/i915.h>
20#include <arch/io.h>
21#include "mainboard.h"
22
23void runio(struct intel_dp *dp, int verbose);
24void runio(struct intel_dp *dp, int verbose)
25{
26 u8 read_val;
27 gtt_write(DDI_BUF_CTL_A,
28 DDI_BUF_IS_IDLE|DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED
29 |0x00000091);
30
31 intel_prepare_ddi();
32
33 gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
34 gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
35 gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
36
37 gtt_write(DEIIR,0x00008000);
38 intel_dp_wait_reg(DEIIR, 0x00000000);
39 gtt_write(DSPSTRIDE(dp->plane), dp->stride);
40 gtt_write(DSPADDR(dp->plane), 0x00000000);
41
42 printk(BIOS_SPEW, "DP_SET_POWER");
43
44 intel_dp_sink_dpms(dp, 0);
45
46 intel_dp_set_m_n_regs(dp);
47
48 intel_dp_get_max_downspread(dp, &read_val);
49
50 intel_dp_set_resolution(dp);
51
52 gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
53 gtt_write(PIPECONF(dp->transcoder),0x00000000);
54 gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
55
56 mainboard_set_port_clk_dp(dp);
57
58 gtt_write(DSPSTRIDE(dp->plane),dp->stride);
Ronald G. Minnich3a75e5e2013-10-28 15:01:54 -0700[diff] [blame]59 gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888);
Ronald G. Minnich9518b562013-09-19 16:45:22 -0700[diff] [blame]60
61 gtt_write(DEIIR,0x00000080);
62 intel_dp_wait_reg(DEIIR, 0x00000000);
63
64 /* There is some reason we removed these three calls from
65 * slippy/gma.c -- I dont remember why!! */
66 gtt_write(PF_WIN_POS(dp->pipe),dp->pfa_pos);
67 gtt_write(PF_CTL(dp->pipe),dp->pfa_ctl);
68 gtt_write(PF_WIN_SZ(dp->pipe),dp->pfa_sz);
69
70 gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
71 gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN);
72
73 /* what is this doing? Not sure yet. But we don't seem to be
74 * able to live without it.*/
75 intel_dp_i2c_write(dp, 0x0);
76 intel_dp_i2c_read(dp, &read_val);
77 intel_dp_i2c_write(dp, 0x04);
78 intel_dp_i2c_read(dp, &read_val);
79 intel_dp_i2c_write(dp, 0x7e);
80 intel_dp_i2c_read(dp, &read_val);
81
82 gtt_write(DDI_BUF_CTL_A,
83 DDI_BUF_IS_IDLE|
84 DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED
85 |0x00000091);
86
87 gtt_write(TRANS_DDI_FUNC_CTL_EDP+0x10,0x00000001);
88 gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE |
89 DP_TP_CTL_ENHANCED_FRAME_ENABLE);
90
91 gtt_write(DDI_BUF_CTL_A,
92 DDI_BUF_CTL_ENABLE|
93 /* another undocumented setting. Surprised? */ 0x40000 |
94 DDI_BUF_IS_IDLE|DDI_A_4_LANES|
95 DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|
96 0x80040091);
97
98 intel_dp_set_bw(dp);
99
100 intel_dp_set_lane_count(dp);
101
102 mainboard_train_link(dp);
103
104 gtt_write(DP_TP_CTL(dp->port),
105 DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE |
106 DP_TP_CTL_LINK_TRAIN_IDLE);
107
108 gtt_write(DP_TP_CTL(dp->port),
109 DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE |
110 DP_TP_CTL_LINK_TRAIN_NORMAL);
111
112 gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
113 gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
114 gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
115
116 /* some of this is not needed. But with a total lack of docs, well ...*/
117 gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE );
118
119 gtt_write(SDEIIR,0x00000000);
120 gtt_write(DEIIR,0x00000000);
121 gtt_write(DEIIR,0x00008000);
122 intel_dp_wait_reg(DEIIR, 0x00000000);
123
124 gtt_write(DSPSTRIDE(dp->plane),dp->stride);
125 gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
126
127 gtt_write(DEIIR,0x00000080);
128 intel_dp_wait_reg(DEIIR, 0x00000000);
129
130 gtt_write(DSPSTRIDE(dp->plane),dp->stride);
Ronald G. Minnich3a75e5e2013-10-28 15:01:54 -0700[diff] [blame]131 gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
Ronald G. Minnich9518b562013-09-19 16:45:22 -0700[diff] [blame]132
133 gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | EDP_BLC_ENABLE | PANEL_POWER_ON);
134
135 gtt_write(SDEIIR,0x00000000);
136 gtt_write(SDEIIR,0x00000000);
137 gtt_write(DEIIR,0x00000000);
138
139}