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review.coreboot.org / coreboot / 9518b56ab079f4c12eefe83cc9b4fa24b413ebe8 / . / src / mainboard / google / peppy / i915io.c
blob: 693aed5185e497d5c6d1a8f47facaa839392abfa [file] [log] [blame]
Ronald G. Minnich9518b562013-09-19 16:45:22 -0700[diff] [blame^]1/*
2* This file is part of the coreboot project.
3*
4* Copyright 2013 Google Inc.
5*
6* This program is free software; you can redistribute it and/or modify
7* it under the terms of the GNU General Public License as published by
8* the Free Software Foundation; version 2 of the License.
9*
10* This program is distributed in the hope that it will be useful,
11* but WITHOUT ANY WARRANTY; without even the implied warranty of
12* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13* GNU General Public License for more details.
14*
15* You should have received a copy of the GNU General Public License
16* along with this program; if not, write to the Free Software
17* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18*/
19
20#include <stdint.h>
21#include <console/console.h>
22#include <delay.h>
23#include <drivers/intel/gma/i915.h>
24#include <arch/io.h>
25#include "mainboard.h"
26
27void runio(struct intel_dp *dp, int verbose);
28void runio(struct intel_dp *dp, int verbose)
29{
30 u8 read_val;
31 gtt_write(DDI_BUF_CTL_A,
32 DDI_BUF_IS_IDLE|DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED
33 |0x00000091);
34
35 intel_prepare_ddi();
36
37 gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
38 gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
39 gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
40
41 gtt_write(DEIIR,0x00008000);
42 intel_dp_wait_reg(DEIIR, 0x00000000);
43 gtt_write(DSPSTRIDE(dp->plane), dp->stride);
44 gtt_write(DSPADDR(dp->plane), 0x00000000);
45
46 printk(BIOS_SPEW, "DP_SET_POWER");
47
48 intel_dp_sink_dpms(dp, 0);
49
50 intel_dp_set_m_n_regs(dp);
51
52 intel_dp_get_max_downspread(dp, &read_val);
53
54 intel_dp_set_resolution(dp);
55
56 gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
57 gtt_write(PIPECONF(dp->transcoder),0x00000000);
58 gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
59
60 mainboard_set_port_clk_dp(dp);
61
62 gtt_write(DSPSTRIDE(dp->plane),dp->stride);
63 gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888);
64
65 gtt_write(DEIIR,0x00000080);
66 intel_dp_wait_reg(DEIIR, 0x00000000);
67
68 /* There is some reason we removed these three calls from
69 * slippy/gma.c -- I dont remember why!! */
70 gtt_write(PF_WIN_POS(dp->pipe),dp->pfa_pos);
71 gtt_write(PF_CTL(dp->pipe),dp->pfa_ctl);
72 gtt_write(PF_WIN_SZ(dp->pipe),dp->pfa_sz);
73
74 gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
75 gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN);
76
77 /* what is this doing? Not sure yet. But we don't seem to be
78 * able to live without it.*/
79 intel_dp_i2c_write(dp, 0x0);
80 intel_dp_i2c_read(dp, &read_val);
81 intel_dp_i2c_write(dp, 0x04);
82 intel_dp_i2c_read(dp, &read_val);
83 intel_dp_i2c_write(dp, 0x7e);
84 intel_dp_i2c_read(dp, &read_val);
85
86 gtt_write(DDI_BUF_CTL_A,
87 DDI_BUF_IS_IDLE|
88 DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED
89 |0x00000091);
90
91 gtt_write(TRANS_DDI_FUNC_CTL_EDP+0x10,0x00000001);
92 gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE |
93 DP_TP_CTL_ENHANCED_FRAME_ENABLE);
94
95 gtt_write(DDI_BUF_CTL_A,
96 DDI_BUF_CTL_ENABLE|
97 /* another undocumented setting. Surprised? */ 0x40000 |
98 DDI_BUF_IS_IDLE|DDI_A_4_LANES|
99 DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|
100 0x80040091);
101
102 intel_dp_set_bw(dp);
103
104 intel_dp_set_lane_count(dp);
105
106 mainboard_train_link(dp);
107
108 gtt_write(DP_TP_CTL(dp->port),
109 DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE |
110 DP_TP_CTL_LINK_TRAIN_IDLE);
111
112 gtt_write(DP_TP_CTL(dp->port),
113 DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE |
114 DP_TP_CTL_LINK_TRAIN_NORMAL);
115
116 gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
117 gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
118 gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
119
120 /* some of this is not needed. But with a total lack of docs, well ...*/
121 gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE );
122
123 gtt_write(SDEIIR,0x00000000);
124 gtt_write(DEIIR,0x00000000);
125 gtt_write(DEIIR,0x00008000);
126 intel_dp_wait_reg(DEIIR, 0x00000000);
127
128 gtt_write(DSPSTRIDE(dp->plane),dp->stride);
129 gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
130
131 gtt_write(DEIIR,0x00000080);
132 intel_dp_wait_reg(DEIIR, 0x00000000);
133
134 gtt_write(DSPSTRIDE(dp->plane),dp->stride);
135 gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_RGBX888);
136
137 gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | EDP_BLC_ENABLE | PANEL_POWER_ON);
138
139 gtt_write(SDEIIR,0x00000000);
140 gtt_write(SDEIIR,0x00000000);
141 gtt_write(DEIIR,0x00000000);
142
143}
144