Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 3 | * |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 17 | #include <stdint.h> |
| 18 | #include <string.h> |
| 19 | #include <arch/io.h> |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 20 | #include <device/pci_def.h> |
| 21 | #include <device/pnp_def.h> |
| 22 | #include <cpu/x86/lapic.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 23 | #include <lib.h> |
Kyösti Mälkki | 12d681b | 2014-06-14 18:51:34 +0300 | [diff] [blame] | 24 | #include <arch/acpi.h> |
Kyösti Mälkki | a7c9611 | 2013-10-13 20:41:57 +0300 | [diff] [blame] | 25 | #include <cbmem.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 26 | #include <pc80/mc146818rtc.h> |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 27 | #include <console/console.h> |
| 28 | #include <cpu/x86/bist.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 29 | #include <halt.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 30 | #include <northbridge/intel/i945/i945.h> |
| 31 | #include <northbridge/intel/i945/raminit.h> |
| 32 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Patrick Georgi | ad0dda7 | 2015-07-13 19:25:01 +0200 | [diff] [blame] | 33 | #include <timestamp.h> |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 34 | #include "option_table.h" |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 35 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 36 | void setup_ich7_gpios(void) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 37 | { |
| 38 | u32 gpios; |
| 39 | |
| 40 | printk(BIOS_DEBUG, " GPIOS..."); |
| 41 | /* General Registers */ |
| 42 | outl(0x1f28f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ |
| 43 | outl(0xe0e809c3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ |
| 44 | // Power On value is eede1fbf, we set: (TODO explain why) |
| 45 | // -- [21] = 1 |
| 46 | // -- [20] = 0 |
| 47 | // -- [18] = 0 |
| 48 | // -- [17] = 0 |
| 49 | // -- [13] = 1 |
| 50 | // -- [05] = 0 |
| 51 | // -- [04] = 0 |
| 52 | // -- [03] = 0 |
| 53 | // -- [02] = 0 |
| 54 | // We should probably do this explicitly bitwise, see below. |
| 55 | outl(0xeee83f83, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 56 | /* Output Control Registers */ |
| 57 | outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ |
| 58 | /* Input Control Registers */ |
| 59 | outl(0x00000180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ |
| 60 | outl(0x000000e6, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ |
| 61 | outl(0x000000d0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ |
| 62 | outl(0x00000034, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ |
| 63 | |
| 64 | printk(BIOS_SPEW, "\n Initializing drive bay...\n"); |
| 65 | gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2 |
| 66 | gpios |= (1 << 0); // GPIO33 = ODD |
| 67 | gpios |= (1 << 1); // GPIO34 = IDE_RST# |
| 68 | outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ |
| 69 | |
| 70 | gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level |
| 71 | gpios &= ~(1 << 13); // ?? |
| 72 | outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 73 | |
| 74 | printk(BIOS_SPEW, "\n Initializing Ethernet NIC...\n"); |
| 75 | gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level |
| 76 | gpios &= ~(1 << 24); // Enable LAN Power |
| 77 | outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 78 | } |
| 79 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 80 | static void ich7_enable_lpc(void) |
| 81 | { |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 82 | int lpt_en = 0; |
Patrick Georgi | b251753 | 2011-05-10 21:53:13 +0000 | [diff] [blame] | 83 | if (read_option(lpt, 0) != 0) { |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 84 | lpt_en = 1<<2; // enable LPT |
| 85 | } |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 86 | // Enable Serial IRQ |
| 87 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); |
| 88 | // decode range |
| 89 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); |
| 90 | // decode range |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 91 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 92 | // Enable 0x02e0 - 0x2ff |
| 93 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1); |
| 94 | // Enable 0x600 - 0x6ff |
| 95 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); |
| 96 | // Enable 0x68 - 0x6f |
| 97 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); |
| 98 | } |
| 99 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 100 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 101 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 102 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 103 | * but safe anyways" method. |
| 104 | */ |
| 105 | static void pnp_enter_ext_func_mode(device_t dev) |
| 106 | { |
| 107 | unsigned int port = dev >> 8; |
| 108 | outb(0x55, port); |
| 109 | } |
| 110 | |
| 111 | static void pnp_exit_ext_func_mode(device_t dev) |
| 112 | { |
| 113 | unsigned int port = dev >> 8; |
| 114 | outb(0xaa, port); |
| 115 | } |
| 116 | |
| 117 | static void pnp_write_register(device_t dev, int reg, int val) |
| 118 | { |
| 119 | unsigned int port = dev >> 8; |
| 120 | outb(reg, port); |
| 121 | outb(val, port+1); |
| 122 | } |
| 123 | |
| 124 | static void early_superio_config(void) |
| 125 | { |
| 126 | device_t dev; |
| 127 | |
| 128 | dev=PNP_DEV(0x4e, 0x00); |
| 129 | |
| 130 | pnp_enter_ext_func_mode(dev); |
| 131 | pnp_write_register(dev, 0x02, 0x0e); // UART power |
| 132 | pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base |
| 133 | pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base |
| 134 | pnp_write_register(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ |
| 135 | pnp_write_register(dev, 0x1e, 1); // no 32khz clock |
| 136 | pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base |
| 137 | pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ |
| 138 | pnp_write_register(dev, 0x2c, 0); // DMA0 FIR |
| 139 | pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base |
| 140 | |
| 141 | pnp_write_register(dev, 0x31, 0xce); // GPIO1 DIR |
| 142 | pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL |
| 143 | pnp_write_register(dev, 0x33, 0x0f); // GPIO2 DIR |
| 144 | pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL |
| 145 | pnp_write_register(dev, 0x35, 0xa8); // GPIO3 DIR |
| 146 | pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL |
| 147 | pnp_write_register(dev, 0x37, 0xa8); // GPIO4 DIR |
| 148 | pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL |
| 149 | |
| 150 | pnp_write_register(dev, 0x39, 0x00); // GPIO1 OUT |
| 151 | pnp_write_register(dev, 0x40, 0x80); // GPIO2/MISC OUT |
| 152 | pnp_write_register(dev, 0x41, 0x00); // GPIO5 OUT |
| 153 | pnp_write_register(dev, 0x42, 0xa8); // GPIO5 DIR |
| 154 | pnp_write_register(dev, 0x43, 0x00); // GPIO5 POL |
| 155 | pnp_write_register(dev, 0x44, 0x00); // GPIO ALT1 |
| 156 | pnp_write_register(dev, 0x45, 0x50); // GPIO ALT2 |
| 157 | pnp_write_register(dev, 0x46, 0x00); // GPIO ALT3 |
| 158 | |
| 159 | pnp_write_register(dev, 0x48, 0x55); // GPIO ALT5 |
| 160 | pnp_write_register(dev, 0x49, 0x55); // GPIO ALT6 |
| 161 | pnp_write_register(dev, 0x4a, 0x55); // GPIO ALT7 |
| 162 | pnp_write_register(dev, 0x4b, 0x55); // GPIO ALT8 |
| 163 | pnp_write_register(dev, 0x4c, 0x55); // GPIO ALT9 |
| 164 | pnp_write_register(dev, 0x4d, 0x55); // GPIO ALT10 |
| 165 | |
| 166 | pnp_exit_ext_func_mode(dev); |
| 167 | } |
| 168 | |
| 169 | static void rcba_config(void) |
| 170 | { |
| 171 | /* Set up virtual channel 0 */ |
| 172 | //RCBA32(0x0014) = 0x80000001; |
| 173 | //RCBA32(0x001c) = 0x03128010; |
| 174 | |
| 175 | /* Device 1f interrupt pin register */ |
| 176 | RCBA32(0x3100) = 0x00042220; |
| 177 | /* Device 1d interrupt pin register */ |
| 178 | RCBA32(0x310c) = 0x00214321; |
| 179 | |
| 180 | /* dev irq route register */ |
| 181 | RCBA16(0x3140) = 0x0232; |
| 182 | RCBA16(0x3142) = 0x3246; |
| 183 | RCBA16(0x3144) = 0x0237; |
| 184 | RCBA16(0x3146) = 0x3201; |
| 185 | RCBA16(0x3148) = 0x3216; |
| 186 | |
| 187 | /* Enable IOAPIC */ |
| 188 | RCBA8(0x31ff) = 0x03; |
| 189 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 190 | /* Disable unused devices */ |
| 191 | RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA; |
| 192 | RCBA32(0x3418) |= (1 << 0); // Required. |
| 193 | |
| 194 | /* Enable PCIe Root Port Clock Gate */ |
| 195 | // RCBA32(0x341c) = 0x00000001; |
| 196 | |
| 197 | |
| 198 | /* This should probably go into the ACPI enable trap */ |
| 199 | /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ |
| 200 | RCBA32(0x1e84) = 0x00020001; |
| 201 | RCBA32(0x1e80) = 0x0000fe01; |
| 202 | |
| 203 | /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ |
| 204 | RCBA32(0x1e9c) = 0x000200f0; |
| 205 | RCBA32(0x1e98) = 0x000c0801; |
| 206 | } |
| 207 | |
| 208 | static void early_ich7_init(void) |
| 209 | { |
| 210 | uint8_t reg8; |
| 211 | uint32_t reg32; |
| 212 | |
| 213 | // program secondary mlt XXX byte? |
| 214 | pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 215 | |
| 216 | // reset rtc power status |
| 217 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 218 | reg8 &= ~(1 << 2); |
| 219 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); |
| 220 | |
| 221 | // usb transient disconnect |
| 222 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 223 | reg8 |= (3 << 0); |
| 224 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 225 | |
| 226 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 227 | reg32 |= (1 << 29) | (1 << 17); |
| 228 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 229 | |
| 230 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 231 | reg32 |= (1 << 31) | (1 << 27); |
| 232 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 233 | |
| 234 | RCBA32(0x0088) = 0x0011d000; |
| 235 | RCBA16(0x01fc) = 0x060f; |
| 236 | RCBA32(0x01f4) = 0x86000040; |
| 237 | RCBA32(0x0214) = 0x10030549; |
| 238 | RCBA32(0x0218) = 0x00020504; |
| 239 | RCBA8(0x0220) = 0xc5; |
| 240 | reg32 = RCBA32(0x3410); |
| 241 | reg32 |= (1 << 6); |
| 242 | RCBA32(0x3410) = reg32; |
| 243 | reg32 = RCBA32(0x3430); |
| 244 | reg32 &= ~(3 << 0); |
| 245 | reg32 |= (1 << 0); |
| 246 | RCBA32(0x3430) = reg32; |
| 247 | RCBA32(0x3418) |= (1 << 0); |
| 248 | RCBA16(0x0200) = 0x2008; |
| 249 | RCBA8(0x2027) = 0x0d; |
| 250 | RCBA16(0x3e08) |= (1 << 7); |
| 251 | RCBA16(0x3e48) |= (1 << 7); |
| 252 | RCBA32(0x3e0e) |= (1 << 7); |
| 253 | RCBA32(0x3e4e) |= (1 << 7); |
| 254 | |
| 255 | // next step only on ich7m b0 and later: |
| 256 | reg32 = RCBA32(0x2034); |
| 257 | reg32 &= ~(0x0f << 16); |
| 258 | reg32 |= (5 << 16); |
| 259 | RCBA32(0x2034) = reg32; |
| 260 | } |
| 261 | |
Aaron Durbin | a0a3727 | 2014-08-14 08:35:11 -0500 | [diff] [blame] | 262 | #include <cpu/intel/romstage.h> |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 263 | void main(unsigned long bist) |
| 264 | { |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 265 | int s3resume = 0; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 266 | |
Patrick Georgi | ad0dda7 | 2015-07-13 19:25:01 +0200 | [diff] [blame] | 267 | timestamp_init(timestamp_get()); |
| 268 | timestamp_add_now(TS_START_ROMSTAGE); |
| 269 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 270 | if (bist == 0) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 271 | enable_lapic(); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 272 | |
| 273 | #if 0 |
| 274 | /* Force PCIRST# */ |
| 275 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); |
Stefan Reinauer | bc8613e | 2010-08-25 18:35:42 +0000 | [diff] [blame] | 276 | udelay(200 * 1000); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 277 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 278 | #endif |
| 279 | |
| 280 | ich7_enable_lpc(); |
| 281 | early_superio_config(); |
| 282 | |
| 283 | /* Set up the console */ |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 284 | console_init(); |
| 285 | |
| 286 | /* Halt if there was a built in self test failure */ |
| 287 | report_bist_failure(bist); |
| 288 | |
| 289 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 290 | printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); |
| 291 | outb(0x6, 0xcf9); |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 292 | halt(); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 293 | } |
| 294 | |
| 295 | /* Perform some early chipset initialization required |
| 296 | * before RAM initialization can work |
| 297 | */ |
| 298 | i945_early_initialization(); |
| 299 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 300 | s3resume = southbridge_detect_s3_resume(); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 301 | |
| 302 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 303 | enable_smbus(); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 304 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 305 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
| 306 | dump_spd_registers(); |
| 307 | #endif |
| 308 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 309 | sdram_initialize(s3resume ? 2 : 0, NULL); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 310 | |
| 311 | /* Perform some initialization that must run before stage2 */ |
| 312 | early_ich7_init(); |
| 313 | |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 314 | /* This should probably go away. Until now it is required |
| 315 | * and mainboard specific |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 316 | */ |
| 317 | rcba_config(); |
| 318 | |
| 319 | /* Chipset Errata! */ |
| 320 | fixup_i945_errata(); |
| 321 | |
| 322 | /* Initialize the internal PCIe links before we go into stage2 */ |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 323 | i945_late_initialization(s3resume); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 324 | } |