zbao | 323a923 | 2012-07-19 16:39:01 +0800 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; version 2 of the License. |
| 9 | # |
| 10 | # This program is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | # GNU General Public License for more details. |
| 14 | # |
zbao | 323a923 | 2012-07-19 16:39:01 +0800 | [diff] [blame] | 15 | chip northbridge/amd/agesa/family15tn/root_complex |
Martin Roth | c89d3da | 2013-01-16 19:18:09 -0700 | [diff] [blame] | 16 | |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 17 | device cpu_cluster 0 on |
Martin Roth | c89d3da | 2013-01-16 19:18:09 -0700 | [diff] [blame] | 18 | chip cpu/amd/agesa/family15tn |
| 19 | device lapic 10 on end |
| 20 | end |
| 21 | end |
| 22 | |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 23 | device domain 0 on |
Martin Roth | c89d3da | 2013-01-16 19:18:09 -0700 | [diff] [blame] | 24 | subsystemid 0x1022 0x1410 inherit |
| 25 | chip northbridge/amd/agesa/family15tn # CPU side of HT root complex |
| 26 | |
| 27 | chip northbridge/amd/agesa/family15tn # PCI side of HT root complex |
| 28 | device pci 0.0 on end # Root Complex |
| 29 | device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX |
| 30 | device pci 1.1 on end # Internal Multimedia |
| 31 | device pci 2.0 on end # PCIE SLOT0 x16 |
Siyuan Wang | 88d0c73 | 2013-04-16 13:59:37 +0800 | [diff] [blame] | 32 | device pci 3.0 off end |
Martin Roth | c89d3da | 2013-01-16 19:18:09 -0700 | [diff] [blame] | 33 | device pci 4.0 on end # PCIE MINI0 |
| 34 | device pci 5.0 on end # PCIE MINI1 |
| 35 | device pci 6.0 on end # PCIE Slot1 x1 |
| 36 | device pci 7.0 on end # LAN |
| 37 | device pci 8.0 off end # NB/SB Link P2P bridge |
| 38 | end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex |
| 39 | |
| 40 | chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus |
| 41 | device pci 10.0 on end # XHCI HC0 |
| 42 | device pci 10.1 on end # XHCI HC1 |
| 43 | device pci 11.0 on end # SATA |
| 44 | device pci 12.0 on end # USB |
| 45 | device pci 12.2 on end # USB |
| 46 | device pci 13.0 on end # USB |
| 47 | device pci 13.2 on end # USB |
| 48 | device pci 14.0 on # SMBUS |
| 49 | chip drivers/generic/generic #dimm 0 |
Martin Roth | 7fb692b | 2013-01-20 10:38:58 -0700 | [diff] [blame] | 50 | device i2c 50 on end # 7-bit SPD address |
Martin Roth | c89d3da | 2013-01-16 19:18:09 -0700 | [diff] [blame] | 51 | end |
| 52 | chip drivers/generic/generic #dimm 1 |
Martin Roth | 7fb692b | 2013-01-20 10:38:58 -0700 | [diff] [blame] | 53 | device i2c 51 on end # 7-bit SPD address |
Martin Roth | c89d3da | 2013-01-16 19:18:09 -0700 | [diff] [blame] | 54 | end |
| 55 | end # SM |
| 56 | device pci 14.1 on end # IDE 0x439c |
| 57 | device pci 14.2 on end # HDA 0x4383 |
| 58 | device pci 14.3 on end # LPC 0x439d |
| 59 | device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. |
| 60 | device pci 14.5 on end # USB 2 |
| 61 | device pci 14.6 off end # Gec |
| 62 | device pci 14.7 on end # SD |
| 63 | device pci 15.0 off end # PCIe 0 |
| 64 | device pci 15.1 off end # PCIe 1 |
| 65 | device pci 15.2 off end # PCIe 2 |
| 66 | device pci 15.3 off end # PCIe 3 |
Martin Roth | c89d3da | 2013-01-16 19:18:09 -0700 | [diff] [blame] | 67 | end #chip southbridge/amd/hudson |
| 68 | |
| 69 | device pci 18.0 on end |
| 70 | device pci 18.1 on end |
| 71 | device pci 18.2 on end |
| 72 | device pci 18.3 on end |
| 73 | device pci 18.4 on end |
| 74 | device pci 18.5 on end |
| 75 | |
Martin Roth | 7fb692b | 2013-01-20 10:38:58 -0700 | [diff] [blame] | 76 | register "spdAddrLookup" = " |
| 77 | { |
| 78 | { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses |
| 79 | { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses |
| 80 | }" |
| 81 | |
Martin Roth | c89d3da | 2013-01-16 19:18:09 -0700 | [diff] [blame] | 82 | end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 83 | end #domain |
Martin Roth | c89d3da | 2013-01-16 19:18:09 -0700 | [diff] [blame] | 84 | end #chip northbridge/amd/agesa/family15tn/root_complex |