Aaron Durbin | e0785c0 | 2013-10-21 12:15:29 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | e0785c0 | 2013-10-21 12:15:29 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef _X86_MP_H_ |
| 17 | #define _X86_MP_H_ |
| 18 | |
| 19 | #include <arch/smp/atomic.h> |
| 20 | |
| 21 | #define CACHELINE_SIZE 64 |
| 22 | |
| 23 | struct cpu_info; |
| 24 | struct bus; |
| 25 | |
| 26 | static inline void mfence(void) |
| 27 | { |
| 28 | __asm__ __volatile__("mfence\t\n": : :"memory"); |
| 29 | } |
| 30 | |
| 31 | typedef void (*mp_callback_t)(void *arg); |
| 32 | |
| 33 | /* |
| 34 | * A mp_flight_record details a sequence of calls for the APs to perform |
| 35 | * along with the BSP to coordinate sequencing. Each flight record either |
| 36 | * provides a barrier for each AP before calling the callback or the APs |
| 37 | * are allowed to perform the callback without waiting. Regardless, each |
| 38 | * record has the cpus_entered field incremented for each record. When |
| 39 | * the BSP observes that the cpus_entered matches the number of APs |
| 40 | * the bsp_call is called with bsp_arg and upon returning releases the |
| 41 | * barrier allowing the APs to make further progress. |
| 42 | * |
| 43 | * Note that ap_call() and bsp_call() can be NULL. In the NULL case the |
| 44 | * callback will just not be called. |
| 45 | */ |
| 46 | struct mp_flight_record { |
| 47 | atomic_t barrier; |
| 48 | atomic_t cpus_entered; |
| 49 | mp_callback_t ap_call; |
| 50 | void *ap_arg; |
| 51 | mp_callback_t bsp_call; |
| 52 | void *bsp_arg; |
| 53 | } __attribute__((aligned(CACHELINE_SIZE))); |
| 54 | |
| 55 | #define _MP_FLIGHT_RECORD(barrier_, ap_func_, ap_arg_, bsp_func_, bsp_arg_) \ |
| 56 | { \ |
| 57 | .barrier = ATOMIC_INIT(barrier_), \ |
| 58 | .cpus_entered = ATOMIC_INIT(0), \ |
| 59 | .ap_call = ap_func_, \ |
| 60 | .ap_arg = ap_arg_, \ |
| 61 | .bsp_call = bsp_func_, \ |
| 62 | .bsp_arg = bsp_arg_, \ |
| 63 | } |
| 64 | |
| 65 | #define MP_FR_BLOCK_APS(ap_func_, ap_arg_, bsp_func_, bsp_arg_) \ |
| 66 | _MP_FLIGHT_RECORD(0, ap_func_, ap_arg_, bsp_func_, bsp_arg_) |
| 67 | |
| 68 | #define MP_FR_NOBLOCK_APS(ap_func_, ap_arg_, bsp_func_, bsp_arg_) \ |
| 69 | _MP_FLIGHT_RECORD(1, ap_func_, ap_arg_, bsp_func_, bsp_arg_) |
| 70 | |
| 71 | /* The mp_params structure provides the arguments to the mp subsystem |
| 72 | * for bringing up APs. */ |
| 73 | struct mp_params { |
| 74 | int num_cpus; /* Total cpus include BSP */ |
| 75 | int parallel_microcode_load; |
| 76 | const void *microcode_pointer; |
| 77 | /* adjust_apic_id() is called for every potential apic id in the |
| 78 | * system up from 0 to CONFIG_MAX_CPUS. Return adjusted apic_id. */ |
| 79 | int (*adjust_apic_id)(int index, int apic_id); |
| 80 | /* Flight plan for APs and BSP. */ |
| 81 | struct mp_flight_record *flight_plan; |
| 82 | int num_records; |
| 83 | }; |
| 84 | |
| 85 | /* |
| 86 | * mp_init() will set up the SIPI vector and bring up the APs according to |
| 87 | * mp_params. Each flight record will be executed according to the plan. Note |
| 88 | * that the MP infrastructure uses SMM default area without saving it. It's |
| 89 | * up to the chipset or mainboard to either e820 reserve this area or save this |
| 90 | * region prior to calling mp_init() and restoring it after mp_init returns. |
| 91 | * |
| 92 | * At the time mp_init() is called the MTRR MSRs are mirrored into APs then |
| 93 | * caching is enabled before running the flight plan. |
| 94 | * |
| 95 | * The MP initialization has the following properties: |
| 96 | * 1. APs are brought up in parallel. |
| 97 | * 2. The ordering of coreboot cpu number and APIC ids is not deterministic. |
| 98 | * Therefore, one cannot rely on this property or the order of devices in |
| 99 | * the device tree unless the chipset or mainboard know the APIC ids |
| 100 | * a priori. |
| 101 | * |
| 102 | * mp_init() returns < 0 on error, 0 on success. |
| 103 | */ |
| 104 | int mp_init(struct bus *cpu_bus, struct mp_params *params); |
| 105 | |
| 106 | /* |
| 107 | * Useful functions to use in flight records when sequencing APs. |
| 108 | */ |
| 109 | |
| 110 | /* Calls cpu_initialize(info->index) which calls the coreboot CPU drivers. */ |
| 111 | void mp_initialize_cpu(void *unused); |
| 112 | |
| 113 | /* Returns apic id for coreboot cpu number or < 0 on failure. */ |
| 114 | int mp_get_apic_id(int cpu_slot); |
| 115 | |
Aaron Durbin | cd3f8ad | 2013-10-21 22:24:40 -0500 | [diff] [blame] | 116 | /* |
| 117 | * SMM helpers to use with initializing CPUs. |
| 118 | */ |
| 119 | |
| 120 | /* Send SMI to self without any serialization. */ |
| 121 | void smm_initiate_relocation_parallel(void); |
| 122 | /* Send SMI to self with single execution. */ |
| 123 | void smm_initiate_relocation(void); |
| 124 | |
Aaron Durbin | e0785c0 | 2013-10-21 12:15:29 -0500 | [diff] [blame] | 125 | #endif /* _X86_MP_H_ */ |