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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / src / console / Kconfig
blob: 73c6b282a3e6e2a0cf6d43c40fbbe9d9edd63302 [file] [log] [blame]
Stefan Reinauer1b342262011-01-05 02:27:53 +0000[diff] [blame]1menu "Console"
Hung-Te Linad173ea2013-02-06 21:24:12 +0800[diff] [blame]2
Gabe Blackfbb11cf2013-06-06 00:21:20 -0700[diff] [blame]3config BOOTBLOCK_CONSOLE
4 bool "Enable early (bootblock) console output."
Martin Roth9c073ed2015-12-06 18:00:20 -0700[diff] [blame]5 depends on ARCH_ARM || ARCH_ARM64 || ARCH_RISCV || ARCH_MIPS
Stefan Reinauerd2f45c62013-06-19 13:42:00 -0700[diff] [blame]6 default n
Gabe Blackfbb11cf2013-06-06 00:21:20 -0700[diff] [blame]7 help
8 Use console during the bootblock if supported
9
Kyösti Mälkki361cd812013-08-12 23:29:57 +0300[diff] [blame]10config SQUELCH_EARLY_SMP
11 bool "Squelch AP CPUs from early console."
12 default y
Kyösti Mälkki361cd812013-08-12 23:29:57 +0300[diff] [blame]13 help
14 When selected only the BSP CPU will output to early console.
15
16 Console drivers have unpredictable behaviour if multiple threads
17 attempt to share the same resources without a spinlock.
18
19 If unsure, say Y.
20
Hung-Te Linad173ea2013-02-06 21:24:12 +0800[diff] [blame]21config CONSOLE_SERIAL
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]22 bool "Serial port console output"
Stefan Reinauer509f7722012-12-07 17:31:37 -0800[diff] [blame]23 default y
Kyösti Mälkkiafa7b132014-02-13 17:16:22 +0200[diff] [blame]24 depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL
Stefan Reinauer509f7722012-12-07 17:31:37 -0800[diff] [blame]25 help
Kyösti Mälkkiafa7b132014-02-13 17:16:22 +0200[diff] [blame]26 Send coreboot debug output to a serial port.
David Hendricks6a503b62012-12-31 17:28:43 -0800[diff] [blame]27
Kyösti Mälkkiafa7b132014-02-13 17:16:22 +0200[diff] [blame]28 The type of serial port driver selected based on your configuration is
29 shown on the following menu line. Supporting multiple different types
30 of UARTs in one build is not supported.
Stefan Reinauer4885daa2011-04-26 23:47:04 +0000[diff] [blame]31
Kyösti Mälkkiafa7b132014-02-13 17:16:22 +0200[diff] [blame]32if CONSOLE_SERIAL
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]33
Kyösti Mälkkiafa7b132014-02-13 17:16:22 +0200[diff] [blame]34 comment "I/O mapped, 8250-compatible"
35 depends on DRIVERS_UART_8250IO
36
37 comment "memory mapped, 8250-compatible"
38 depends on DRIVERS_UART_8250MEM
39
40 comment "device-specific UART"
Hung-Te Linad173ea2013-02-06 21:24:12 +0800[diff] [blame]41 depends on HAVE_UART_SPECIAL
Stefan Reinauer509f7722012-12-07 17:31:37 -0800[diff] [blame]42
Kyösti Mälkki70342a72014-03-14 22:28:29 +0200[diff] [blame]43config UART_FOR_CONSOLE
Kyösti Mälkkid5403772014-05-01 00:02:43 +0300[diff] [blame]44 int "Index for UART port to use for console"
Kyösti Mälkki70342a72014-03-14 22:28:29 +0200[diff] [blame]45 default 0
Martin Rothac76ed92015-11-19 11:40:43 -0700[diff] [blame]46 help
47 Select an I/O port to use for serial console:
48 0 = 0x3f8, 1 = 0x2f8, 2 = 0x3e8, 3 = 0x2e8
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]49
Kyösti Mälkki70342a72014-03-14 22:28:29 +0200[diff] [blame]50# FIXME: Early programming in romstage is incorrect as we should
51# program different LDN to actually change the physical port.
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]52config TTYS0_BASE
53 hex
Gabe Black77ffa0d2013-09-30 21:25:49 -0700[diff] [blame]54 depends on DRIVERS_UART
Kyösti Mälkki70342a72014-03-14 22:28:29 +0200[diff] [blame]55 default 0x3f8 if UART_FOR_CONSOLE = 0
56 default 0x2f8 if UART_FOR_CONSOLE = 1
57 default 0x3e8 if UART_FOR_CONSOLE = 2
58 default 0x2e8 if UART_FOR_CONSOLE = 3
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]59 help
Kyösti Mälkki70342a72014-03-14 22:28:29 +0200[diff] [blame]60 Map the COM port number to the respective I/O port.
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]61
Martin Rothac76ed92015-11-19 11:40:43 -0700[diff] [blame]62comment "Serial port base address = 0x3f8"
63depends on UART_FOR_CONSOLE = 0
64comment "Serial port base address = 0x2f8"
65depends on UART_FOR_CONSOLE = 1
66comment "Serial port base address = 0x3e8"
67depends on UART_FOR_CONSOLE = 2
68comment "Serial port base address = 0x2e8"
69depends on UART_FOR_CONSOLE = 3
70
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]71choice
Uwe Hermanna081a3b2009-10-26 23:52:34 +0000[diff] [blame]72 prompt "Baud rate"
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]73 default CONSOLE_SERIAL_115200
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]74
75config CONSOLE_SERIAL_115200
76 bool "115200"
77 help
Uwe Hermanna081a3b2009-10-26 23:52:34 +0000[diff] [blame]78 Set serial port Baud rate to 115200.
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]79config CONSOLE_SERIAL_57600
80 bool "57600"
81 help
Uwe Hermanna081a3b2009-10-26 23:52:34 +0000[diff] [blame]82 Set serial port Baud rate to 57600.
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]83config CONSOLE_SERIAL_38400
84 bool "38400"
85 help
Uwe Hermanna081a3b2009-10-26 23:52:34 +0000[diff] [blame]86 Set serial port Baud rate to 38400.
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]87config CONSOLE_SERIAL_19200
88 bool "19200"
89 help
Uwe Hermanna081a3b2009-10-26 23:52:34 +0000[diff] [blame]90 Set serial port Baud rate to 19200.
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]91config CONSOLE_SERIAL_9600
92 bool "9600"
93 help
Uwe Hermanna081a3b2009-10-26 23:52:34 +0000[diff] [blame]94 Set serial port Baud rate to 9600.
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]95
96endchoice
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]97
Stefan Reinauer509f7722012-12-07 17:31:37 -0800[diff] [blame]98#FIXME(dhendrix): Change name to SERIAL_BAUD? (Stefan sayz: yes!!)
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]99config TTYS0_BAUD
Uwe Hermannd12b7032009-10-16 22:39:55 +0000[diff] [blame]100 int
101 default 115200 if CONSOLE_SERIAL_115200
102 default 57600 if CONSOLE_SERIAL_57600
103 default 38400 if CONSOLE_SERIAL_38400
104 default 19200 if CONSOLE_SERIAL_19200
105 default 9600 if CONSOLE_SERIAL_9600
106 help
Uwe Hermanna081a3b2009-10-26 23:52:34 +0000[diff] [blame]107 Map the Baud rates to an integer.
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]108
Uwe Hermann168b11b2009-10-07 16:15:40 +0000[diff] [blame]109# TODO: Allow user-friendly selection of settings other than 8n1.
Patrick Georgi0e9a9252009-10-06 20:48:07 +0000[diff] [blame]110config TTYS0_LCS
111 int
112 default 3
Kyösti Mälkkiafa7b132014-02-13 17:16:22 +0200[diff] [blame]113 depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM
114
115endif # CONSOLE_SERIAL
Patrick Georgi0e9a9252009-10-06 20:48:07 +0000[diff] [blame]116
Vladimir Serbinenko45988da2013-03-30 02:02:13 +0100[diff] [blame]117config SPKMODEM
118 bool "spkmodem (console on speaker) console output"
119 default n
120 help
121 Send coreboot debug output through speaker
122
Kyösti Mälkkiab94bbf2014-02-25 12:06:14 +0200[diff] [blame]123config CONSOLE_USB
124 bool "USB dongle console output"
125 depends on USBDEBUG
Kyösti Mälkki8101aa62013-08-15 16:27:06 +0300[diff] [blame]126 default n
Uwe Hermann168b11b2009-10-07 16:15:40 +0000[diff] [blame]127 help
Kyösti Mälkkiab94bbf2014-02-25 12:06:14 +0200[diff] [blame]128 Send coreboot debug output to USB.
Uwe Hermann168b11b2009-10-07 16:15:40 +0000[diff] [blame]129
Kyösti Mälkkiab94bbf2014-02-25 12:06:14 +0200[diff] [blame]130 Configuration for USB hardware is under menu Generic Drivers.
Kyösti Mälkkid2dac0a2013-08-23 23:33:16 +0300[diff] [blame]131
Uwe Hermann168b11b2009-10-07 16:15:40 +0000[diff] [blame]132# TODO: Deps?
133# TODO: Improve description.
Stefan Reinauerabc0c852010-11-22 08:09:50 +0000[diff] [blame]134config ONBOARD_VGA_IS_PRIMARY
Uwe Hermann168b11b2009-10-07 16:15:40 +0000[diff] [blame]135 bool "Use onboard VGA as primary video device"
Myles Watson45bb25f2009-09-22 18:49:08 +0000[diff] [blame]136 default n
137 help
138 If not selected, the last adapter found will be used.
139
Rudolf Marek4aa93cc2010-07-16 20:02:09 +0000[diff] [blame]140config CONSOLE_NE2K
141 bool "Network console over NE2000 compatible Ethernet adapter"
142 default n
143 help
144 Send coreboot debug output to a Ethernet console, it works
145 same way as Linux netconsole, packets are received to UDP
146 port 6666 on IP/MAC specified with options bellow.
147 Use following netcat command: nc -u -l -p 6666
148
149config CONSOLE_NE2K_DST_MAC
150 depends on CONSOLE_NE2K
151 string "Destination MAC address of remote system"
152 default "00:13:d4:76:a2:ac"
153 help
154 Type in either MAC address of logging system or MAC address
155 of the router.
156
157config CONSOLE_NE2K_DST_IP
158 depends on CONSOLE_NE2K
159 string "Destination IP of logging system"
160 default "10.0.1.27"
161 help
Daniele Forsi53847a22014-07-22 18:00:56 +0200[diff] [blame]162 This is IP address of the system running for example
Rudolf Marek4aa93cc2010-07-16 20:02:09 +0000[diff] [blame]163 netcat command to dump the packets.
164
165config CONSOLE_NE2K_SRC_IP
166 depends on CONSOLE_NE2K
Stefan Reinauerd6b4f1c2010-09-23 18:29:40 +0000[diff] [blame]167 string "IP address of coreboot system"
Rudolf Marek4aa93cc2010-07-16 20:02:09 +0000[diff] [blame]168 default "10.0.1.253"
169 help
Stefan Reinauerd6b4f1c2010-09-23 18:29:40 +0000[diff] [blame]170 This is the IP of the coreboot system
Rudolf Marek4aa93cc2010-07-16 20:02:09 +0000[diff] [blame]171
172config CONSOLE_NE2K_IO_PORT
173 depends on CONSOLE_NE2K
174 hex "NE2000 adapter fixed IO port address"
175 default 0xe00
176 help
177 This is the IO port address for the IO port
178 on the card, please select some non-conflicting region,
179 32 bytes of IO spaces will be used (and align on 32 bytes
180 boundary, qemu needs broader align)
181
Vadim Bendeburyc34b4632011-09-28 13:51:30 -0700[diff] [blame]182config CONSOLE_CBMEM
Vadim Bendeburyc34b4632011-09-28 13:51:30 -0700[diff] [blame]183 bool "Send console output to a CBMEM buffer"
Paul Menzel60ef4562014-03-08 10:46:52 +0100[diff] [blame]184 default y
Vadim Bendeburyc34b4632011-09-28 13:51:30 -0700[diff] [blame]185 help
186 Enable this to save the console output in a CBMEM buffer. This would
187 allow to see coreboot console output from Linux space.
188
Kyösti Mälkki8659e402014-12-21 08:55:47 +0200[diff] [blame]189if CONSOLE_CBMEM
190
Vadim Bendeburyc34b4632011-09-28 13:51:30 -0700[diff] [blame]191config CONSOLE_CBMEM_BUFFER_SIZE
Vadim Bendeburyc34b4632011-09-28 13:51:30 -0700[diff] [blame]192 hex "Room allocated for console output in CBMEM"
Vladimir Serbinenkoeb67a042014-09-13 20:55:58 +0200[diff] [blame]193 default 0x20000
Vadim Bendeburyc34b4632011-09-28 13:51:30 -0700[diff] [blame]194 help
195 Space allocated for console output storage in CBMEM. The default
Vladimir Serbinenkoeb67a042014-09-13 20:55:58 +0200[diff] [blame]196 value (128K or 0x20000 bytes) is large enough to accommodate
Vadim Bendeburyc34b4632011-09-28 13:51:30 -0700[diff] [blame]197 even the BIOS_SPEW level.
198
Vadim Bendebury6e20e2f2015-04-10 18:04:04 -0700[diff] [blame]199config CONSOLE_CBMEM_DUMP_TO_UART
200 depends on !CONSOLE_SERIAL
201 bool "Dump CBMEM console on resets"
202 default n
203 help
204 Enable this to have CBMEM console buffer contents dumped on the
205 serial output in case serial console is disabled and the device
206 resets itself while trying to boot the payload.
207
Kyösti Mälkki8659e402014-12-21 08:55:47 +0200[diff] [blame]208endif
209
Gerd Hoffmannd7c6e442013-05-30 10:32:31 +0200[diff] [blame]210config CONSOLE_QEMU_DEBUGCON
Gerd Hoffmann038aa292013-05-29 13:06:22 +0200[diff] [blame]211 bool "QEMU debug console output"
212 depends on BOARD_EMULATION_QEMU_X86
213 default y
214 help
215 Send coreboot debug output to QEMU's isa-debugcon device:
216
217 qemu-system-x86_64 \
218 -chardev file,id=debugcon,path=/dir/file.log \
219 -device isa-debugcon,iobase=0x402,chardev=debugcon
220
Gerd Hoffmannd7c6e442013-05-30 10:32:31 +0200[diff] [blame]221config CONSOLE_QEMU_DEBUGCON_PORT
Gerd Hoffmann038aa292013-05-29 13:06:22 +0200[diff] [blame]222 hex "QEMU debug console port"
Gerd Hoffmannd7c6e442013-05-30 10:32:31 +0200[diff] [blame]223 depends on CONSOLE_QEMU_DEBUGCON
Gerd Hoffmann038aa292013-05-29 13:06:22 +0200[diff] [blame]224 default 0x402
225
Martin Roth3a543182015-09-28 15:27:24 -0600[diff] [blame]226config SPI_CONSOLE
227 bool "SPI debug console output"
228 depends on HAVE_SPI_CONSOLE_SUPPORT && !DEBUG_SPI_FLASH
229 help
230 Enable support for the debug console on the Dediprog EM100Pro.
231 This is currently working only in ramstage due to how the spi
232 drivers are written.
233
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]234choice
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]235 prompt "Default console log level"
236 default DEFAULT_CONSOLE_LOGLEVEL_8
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]237
238config DEFAULT_CONSOLE_LOGLEVEL_8
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]239 bool "8: SPEW"
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]240 help
241 Way too many details.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]242config DEFAULT_CONSOLE_LOGLEVEL_7
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]243 bool "7: DEBUG"
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]244 help
245 Debug-level messages.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]246config DEFAULT_CONSOLE_LOGLEVEL_6
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]247 bool "6: INFO"
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]248 help
249 Informational messages.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]250config DEFAULT_CONSOLE_LOGLEVEL_5
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]251 bool "5: NOTICE"
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]252 help
253 Normal but significant conditions.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]254config DEFAULT_CONSOLE_LOGLEVEL_4
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]255 bool "4: WARNING"
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]256 help
257 Warning conditions.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]258config DEFAULT_CONSOLE_LOGLEVEL_3
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]259 bool "3: ERR"
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]260 help
261 Error conditions.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]262config DEFAULT_CONSOLE_LOGLEVEL_2
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]263 bool "2: CRIT"
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]264 help
265 Critical conditions.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]266config DEFAULT_CONSOLE_LOGLEVEL_1
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]267 bool "1: ALERT"
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]268 help
269 Action must be taken immediately.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]270config DEFAULT_CONSOLE_LOGLEVEL_0
Myles Watson03646182009-10-16 19:29:45 +0000[diff] [blame]271 bool "0: EMERG"
272 help
273 System is unusable.
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]274
275endchoice
276
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]277config DEFAULT_CONSOLE_LOGLEVEL
Uwe Hermann7fe41912009-10-11 13:35:24 +0000[diff] [blame]278 int
279 default 0 if DEFAULT_CONSOLE_LOGLEVEL_0
280 default 1 if DEFAULT_CONSOLE_LOGLEVEL_1
281 default 2 if DEFAULT_CONSOLE_LOGLEVEL_2
282 default 3 if DEFAULT_CONSOLE_LOGLEVEL_3
283 default 4 if DEFAULT_CONSOLE_LOGLEVEL_4
284 default 5 if DEFAULT_CONSOLE_LOGLEVEL_5
285 default 6 if DEFAULT_CONSOLE_LOGLEVEL_6
286 default 7 if DEFAULT_CONSOLE_LOGLEVEL_7
287 default 8 if DEFAULT_CONSOLE_LOGLEVEL_8
288 help
289 Map the log level config names to an integer.
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]290
Stefan Reinauerc719f1a2010-03-30 09:57:28 +0000[diff] [blame]291config NO_POST
292 bool "Don't show any POST codes"
293 default n
294
Duncan Laurieb6e97b12012-09-09 19:09:56 -0700[diff] [blame]295config CMOS_POST
296 bool "Store post codes in CMOS for debugging"
Stefan Reinauerc2d5a162012-12-06 14:25:27 -0800[diff] [blame]297 depends on !NO_POST && PC80_SYSTEM
Duncan Laurieb6e97b12012-09-09 19:09:56 -0700[diff] [blame]298 default n
299 help
300 If enabled, coreboot will store post codes in CMOS and switch between
301 two offsets on each boot so the last post code in the previous boot
302 can be retrieved. This uses 3 bytes of CMOS.
303
304config CMOS_POST_OFFSET
305 hex "Offset into CMOS to store POST codes"
306 depends on CMOS_POST
307 default 0
308 help
309 If CMOS_POST is enabled then an offset into CMOS must be provided.
310 If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
311 defined in the mainboard option table.
312
Duncan Lauried5686fe2013-06-10 10:21:41 -0700[diff] [blame]313config CMOS_POST_EXTRA
314 bool "Store extra logging info into CMOS"
315 depends on CMOS_POST
316 default n
317 help
318 This will enable extra logging of work that happens between post
319 codes into CMOS for debug. This uses an additional 8 bytes of CMOS.
320
Daniele Forsiad488d22014-07-30 12:23:35 +0200[diff] [blame]321config CONSOLE_POST
Idwer Vollering5809a732014-03-11 15:36:21 +0000[diff] [blame]322 bool "Show POST codes on the debug console"
323 depends on !NO_POST
324 default n
325 help
326 If enabled, coreboot will additionally print POST codes (which are
327 usually displayed using a so-called "POST card" ISA/PCI/PCI-E
328 device) on the debug console.
329
330config POST_DEVICE
331 bool "Send POST codes to an external device"
332 depends on !NO_POST
333 default y
334
335choice
336 prompt "Device to send POST codes to"
337 depends on POST_DEVICE
338 default POST_DEVICE_NONE
339
340config POST_DEVICE_NONE
341 bool "None"
342config POST_DEVICE_LPC
343 bool "LPC"
344config POST_DEVICE_PCI_PCIE
345 bool "PCI/PCIe"
346endchoice
347
348config POST_IO
David Hendricks6b908d02012-11-05 12:34:09 -0800[diff] [blame]349 bool "Send POST codes to an IO port"
Idwer Vollering5809a732014-03-11 15:36:21 +0000[diff] [blame]350 depends on PC80_SYSTEM && !NO_POST
David Hendricks6b908d02012-11-05 12:34:09 -0800[diff] [blame]351 default y
352 help
353 If enabled, POST codes will be written to an IO port.
Stefan Reinauerc719f1a2010-03-30 09:57:28 +0000[diff] [blame]354
Idwer Vollering5809a732014-03-11 15:36:21 +0000[diff] [blame]355config POST_IO_PORT
356 depends on POST_IO
David Hendricks6b908d02012-11-05 12:34:09 -0800[diff] [blame]357 hex "IO port for POST codes"
358 default 0x80
359 help
360 POST codes on x86 are typically written to the LPC bus on port
Daniele Forsi53847a22014-07-22 18:00:56 +0200[diff] [blame]361 0x80. However, it may be desirable to change the port number
David Hendricks6b908d02012-11-05 12:34:09 -0800[diff] [blame]362 depending on the presence of coprocessors/microcontrollers or if the
363 platform does not support IO in the conventional x86 manner.
364
Martin Roth14554372015-11-12 14:02:42 -0700[diff] [blame]365config NO_EARLY_BOOTBLOCK_POSTCODES
366 def_bool n
367 help
368 Some chipsets require that the routing for the port 80h POST
369 code be configured before any POST codes are sent out.
370 This can be done in the boot block, but there are a couple of
371 POST codes that go out before the chipset's bootblock initialization
372 can happen. This option suppresses those POST codes.
373
David Hendricks6b908d02012-11-05 12:34:09 -0800[diff] [blame]374endmenu