Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 1 | # TODO These two options look too similar |
Kyösti Mälkki | 5c3f384 | 2014-05-08 15:27:15 +0300 | [diff] [blame] | 2 | config PARALLEL_CPU_INIT |
Sven Schnelle | a2701c6 | 2012-07-29 17:42:52 +0200 | [diff] [blame] | 3 | bool |
Kyösti Mälkki | 5c3f384 | 2014-05-08 15:27:15 +0300 | [diff] [blame] | 4 | default n |
Sven Schnelle | a2701c6 | 2012-07-29 17:42:52 +0200 | [diff] [blame] | 5 | |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 6 | config PARALLEL_MP |
| 7 | def_bool n |
| 8 | help |
| 9 | This option uses common MP infrastructure for bringing up APs |
| 10 | in parallel. It additionally provides a more flexible mechanism |
| 11 | for sequencing the steps of bringing up the APs. |
| 12 | |
Aaron Durbin | b21e362 | 2016-12-07 00:32:19 -0600 | [diff] [blame] | 13 | config PARALLEL_MP_AP_WORK |
| 14 | def_bool n |
| 15 | depends on PARALLEL_MP |
| 16 | help |
| 17 | Allow APs to do other work after initialization instead of going |
| 18 | to sleep. |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 19 | |
Patrick Georgi | 0e9a925 | 2009-10-06 20:48:07 +0000 | [diff] [blame] | 20 | config UDELAY_LAPIC |
| 21 | bool |
| 22 | default n |
| 23 | |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 24 | config LAPIC_MONOTONIC_TIMER |
| 25 | def_bool n |
| 26 | depends on UDELAY_LAPIC |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 27 | help |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 28 | Expose monotonic time using the local APIC. |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 29 | |
Patrick Georgi | e135ac5 | 2012-11-20 11:53:47 +0100 | [diff] [blame] | 30 | config UDELAY_LAPIC_FIXED_FSB |
| 31 | int |
| 32 | |
Ronald G. Minnich | 669c4a9 | 2009-08-29 03:00:51 +0000 | [diff] [blame] | 33 | config UDELAY_TSC |
| 34 | bool |
| 35 | default n |
| 36 | |
Kyösti Mälkki | 0d6ddf8 | 2019-10-31 14:52:20 +0200 | [diff] [blame] | 37 | config UNKNOWN_TSC_RATE |
| 38 | bool |
| 39 | default y if LAPIC_MONOTONIC_TIMER |
Aaron Durbin | 8e73b5d | 2013-05-01 15:27:09 -0500 | [diff] [blame] | 40 | |
Aaron Durbin | e850164 | 2013-04-29 22:22:55 -0500 | [diff] [blame] | 41 | config TSC_MONOTONIC_TIMER |
| 42 | def_bool n |
| 43 | depends on UDELAY_TSC |
Aaron Durbin | e850164 | 2013-04-29 22:22:55 -0500 | [diff] [blame] | 44 | help |
| 45 | Expose monotonic time using the TSC. |
| 46 | |
Stefan Reinauer | 0db6820 | 2012-08-07 14:44:51 -0700 | [diff] [blame] | 47 | config TSC_SYNC_LFENCE |
| 48 | bool |
| 49 | default n |
| 50 | help |
| 51 | The CPU driver should select this if the CPU needs |
| 52 | to execute an lfence instruction in order to synchronize |
| 53 | rdtsc. This is true for all modern AMD CPUs. |
| 54 | |
| 55 | config TSC_SYNC_MFENCE |
| 56 | bool |
| 57 | default n |
| 58 | help |
| 59 | The CPU driver should select this if the CPU needs |
| 60 | to execute an mfence instruction in order to synchronize |
| 61 | rdtsc. This is true for all modern Intel CPUs. |
| 62 | |
Aaron Durbin | ef10529 | 2016-05-05 10:34:22 -0500 | [diff] [blame] | 63 | config NO_FIXED_XIP_ROM_SIZE |
| 64 | bool |
| 65 | default n |
| 66 | help |
| 67 | The XIP_ROM_SIZE Kconfig variable is used globally on x86 |
| 68 | with the assumption that all chipsets utilize this value. |
| 69 | For the chipsets which do not use the variable it can lead |
| 70 | to unnecessary alignment constraints in cbfs for romstage. |
| 71 | Therefore, allow those chipsets a path to not be burdened. |
| 72 | |
Uwe Hermann | f9d4c2b | 2009-08-25 12:19:28 +0000 | [diff] [blame] | 73 | config XIP_ROM_SIZE |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 74 | hex |
Aaron Durbin | ef10529 | 2016-05-05 10:34:22 -0500 | [diff] [blame] | 75 | depends on !NO_FIXED_XIP_ROM_SIZE |
Patrick Georgi | f1ce6f2 | 2010-04-12 09:50:53 +0000 | [diff] [blame] | 76 | default 0x10000 |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 77 | |
Arthur Heymans | 47be2d9 | 2019-10-12 17:32:09 +0200 | [diff] [blame] | 78 | config SETUP_XIP_CACHE |
| 79 | bool |
Arthur Heymans | 47be2d9 | 2019-10-12 17:32:09 +0200 | [diff] [blame] | 80 | depends on !NO_XIP_EARLY_STAGES |
| 81 | help |
| 82 | Select this option to set up an MTRR to cache XIP stages loaded |
| 83 | from the bootblock. This is useful on platforms lacking a |
| 84 | non-eviction mode and therefore need to be careful to avoid |
| 85 | eviction. |
| 86 | |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 87 | config CPU_ADDR_BITS |
| 88 | int |
| 89 | default 36 |
| 90 | |
| 91 | config LOGICAL_CPUS |
| 92 | bool |
| 93 | default y |
| 94 | |
Kyösti Mälkki | 4d372c7 | 2019-07-08 13:48:57 +0300 | [diff] [blame] | 95 | config HAVE_SMI_HANDLER |
| 96 | bool |
| 97 | default n |
| 98 | depends on (SMM_ASEG || SMM_TSEG) |
| 99 | |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 100 | config NO_SMM |
Kyösti Mälkki | 4d372c7 | 2019-07-08 13:48:57 +0300 | [diff] [blame] | 101 | bool |
| 102 | default n |
| 103 | |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 104 | config SMM_ASEG |
Duncan Laurie | 8bb7723 | 2012-01-09 22:11:25 -0800 | [diff] [blame] | 105 | bool |
| 106 | default n |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 107 | depends on !NO_SMM |
| 108 | |
| 109 | config SMM_TSEG |
| 110 | bool |
| 111 | default y |
| 112 | depends on !(NO_SMM || SMM_ASEG) |
| 113 | |
| 114 | if SMM_TSEG |
Aaron Durbin | 50a3464 | 2013-01-03 17:38:47 -0600 | [diff] [blame] | 115 | |
| 116 | config SMM_MODULE_HEAP_SIZE |
| 117 | hex |
| 118 | default 0x4000 |
Aaron Durbin | 50a3464 | 2013-01-03 17:38:47 -0600 | [diff] [blame] | 119 | help |
| 120 | This option determines the size of the heap within the SMM handler |
| 121 | modules. |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 122 | |
Raul E Rangel | d3b8393 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 123 | config SMM_MODULE_STACK_SIZE |
| 124 | hex |
| 125 | default 0x400 |
Raul E Rangel | d3b8393 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 126 | help |
| 127 | This option determines the size of the stack within the SMM handler |
| 128 | modules. |
| 129 | |
Marshall Dawson | 46fc6847 | 2018-10-25 13:01:55 -0600 | [diff] [blame] | 130 | config SMM_STUB_STACK_SIZE |
| 131 | hex |
| 132 | default 0x400 |
Marshall Dawson | 46fc6847 | 2018-10-25 13:01:55 -0600 | [diff] [blame] | 133 | help |
| 134 | This option determines the size of the stack within the SMM handler |
| 135 | modules. |
| 136 | |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 137 | endif |
| 138 | |
Patrick Georgi | ce2564a | 2015-09-05 20:21:24 +0200 | [diff] [blame] | 139 | config SMM_LAPIC_REMAP_MITIGATION |
| 140 | bool |
| 141 | default y if NORTHBRIDGE_INTEL_I945 |
| 142 | default y if NORTHBRIDGE_INTEL_GM45 |
| 143 | default y if NORTHBRIDGE_INTEL_NEHALEM |
| 144 | default n |
| 145 | |
Damien Zammit | 149c4c5 | 2015-11-28 21:27:05 +1100 | [diff] [blame] | 146 | config SERIALIZED_SMM_INITIALIZATION |
| 147 | bool |
| 148 | default n |
| 149 | help |
| 150 | On some CPUs, there is a race condition in SMM. |
| 151 | This can occur when both hyperthreads change SMM state |
| 152 | variables in parallel without coordination. |
| 153 | Setting this option serializes the SMM initialization |
| 154 | to avoid an ugly hang in the boot process at the cost |
| 155 | of a slightly longer boot time. |
| 156 | |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 157 | config X86_AMD_FIXED_MTRRS |
| 158 | bool |
| 159 | default n |
| 160 | help |
| 161 | This option informs the MTRR code to use the RdMem and WrMem fields |
| 162 | in the fixed MTRR MSRs. |
Aaron Durbin | e0785c0 | 2013-10-21 12:15:29 -0500 | [diff] [blame] | 163 | |
Marshall Dawson | 98f43a1 | 2019-08-05 16:18:56 -0600 | [diff] [blame] | 164 | config X86_AMD_INIT_SIPI |
| 165 | bool |
| 166 | default n |
| 167 | help |
| 168 | This option limits the number of SIPI signals sent during during the |
| 169 | common AP setup. Intel documentation specifies an INIT SIPI SIPI |
| 170 | sequence, however this doesn't work on some AMD platforms. |
| 171 | |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 172 | config SOC_SETS_MSRS |
| 173 | bool |
| 174 | default n |
| 175 | help |
| 176 | The SoC requires different access methods for reading and writing |
| 177 | the MSRs. Use SoC specific routines to handle the MSR access. |