Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
| 5 | * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) |
| 6 | * Copyright (C) 2007-2008 coresystems GmbH |
| 7 | * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <cpu/x86/mtrr.h> |
| 20 | #include <cpu/x86/cache.h> |
| 21 | #include <cpu/x86/post_code.h> |
| 22 | #include <cpu/x86/lapic_def.h> |
| 23 | |
| 24 | /* Macro to access Local APIC registers at default base. */ |
| 25 | #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) |
| 26 | #define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) |
| 27 | |
| 28 | #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE |
| 29 | #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |
| 30 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 31 | .global bootblock_pre_c_entry |
| 32 | |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 33 | .code32 |
| 34 | _cache_as_ram_setup: |
| 35 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 36 | bootblock_pre_c_entry: |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 37 | |
| 38 | cache_as_ram: |
| 39 | post_code(0x20) |
| 40 | |
| 41 | movl $LAPIC_BASE_MSR, %ecx |
| 42 | rdmsr |
| 43 | andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax |
| 44 | jz ap_init |
| 45 | |
| 46 | /* Clear/disable fixed MTRRs */ |
| 47 | mov $fixed_mtrr_list_size, %ebx |
| 48 | xor %eax, %eax |
| 49 | xor %edx, %edx |
| 50 | |
| 51 | clear_fixed_mtrr: |
| 52 | add $-2, %ebx |
| 53 | movzwl fixed_mtrr_list(%ebx), %ecx |
| 54 | wrmsr |
| 55 | jnz clear_fixed_mtrr |
| 56 | |
Elyes HAOUAS | 02820ca | 2018-09-30 07:44:39 +0200 | [diff] [blame] | 57 | /* Figure out how many MTRRs we have, and clear them out */ |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 58 | mov $MTRR_CAP_MSR, %ecx |
| 59 | rdmsr |
| 60 | movzb %al, %ebx /* Number of variable MTRRs */ |
| 61 | mov $MTRR_PHYS_BASE(0), %ecx |
| 62 | xor %eax, %eax |
| 63 | xor %edx, %edx |
| 64 | |
| 65 | clear_var_mtrr: |
| 66 | wrmsr |
| 67 | inc %ecx |
| 68 | wrmsr |
| 69 | inc %ecx |
| 70 | dec %ebx |
| 71 | jnz clear_var_mtrr |
| 72 | post_code(0x21) |
| 73 | |
| 74 | /* Configure the default memory type to uncacheable. */ |
| 75 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 76 | rdmsr |
| 77 | andl $(~0x00000cff), %eax |
| 78 | wrmsr |
| 79 | |
| 80 | post_code(0x22) |
| 81 | |
| 82 | /* Determine CPU_ADDR_BITS and load PHYSMASK high |
| 83 | * word to %edx. |
| 84 | */ |
| 85 | movl $0x80000000, %eax |
| 86 | cpuid |
| 87 | cmpl $0x80000008, %eax |
| 88 | jc addrsize_no_MSR |
| 89 | movl $0x80000008, %eax |
| 90 | cpuid |
| 91 | movb %al, %cl |
| 92 | sub $32, %cl |
| 93 | movl $1, %edx |
| 94 | shl %cl, %edx |
| 95 | subl $1, %edx |
| 96 | jmp addrsize_set_high |
| 97 | addrsize_no_MSR: |
| 98 | movl $1, %eax |
| 99 | cpuid |
| 100 | andl $(1 << 6 | 1 << 17), %edx /* PAE or PSE36 */ |
| 101 | jz addrsize_set_high |
| 102 | movl $0x0f, %edx |
| 103 | |
| 104 | /* Preload high word of address mask (in %edx) for Variable |
| 105 | * MTRRs 0 and 1 and enable local APIC at default base. |
| 106 | */ |
| 107 | addrsize_set_high: |
| 108 | xorl %eax, %eax |
| 109 | movl $MTRR_PHYS_MASK(0), %ecx |
| 110 | wrmsr |
| 111 | movl $MTRR_PHYS_MASK(1), %ecx |
| 112 | wrmsr |
| 113 | movl $LAPIC_BASE_MSR, %ecx |
| 114 | not %edx |
| 115 | movl %edx, %ebx |
| 116 | rdmsr |
| 117 | andl %ebx, %edx |
| 118 | andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax |
| 119 | orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax |
| 120 | wrmsr |
| 121 | |
| 122 | bsp_init: |
| 123 | |
| 124 | post_code(0x23) |
| 125 | |
| 126 | /* Send INIT IPI to all excluding ourself. */ |
| 127 | movl LAPIC(ICR), %edi |
| 128 | movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax |
| 129 | 1: movl %eax, (%edi) |
| 130 | movl $0x30, %ecx |
| 131 | 2: pause |
| 132 | dec %ecx |
| 133 | jnz 2b |
| 134 | movl (%edi), %ecx |
| 135 | andl $LAPIC_ICR_BUSY, %ecx |
| 136 | jnz 1b |
| 137 | |
| 138 | post_code(0x24) |
| 139 | |
| 140 | movl $1, %eax |
| 141 | cpuid |
| 142 | btl $28, %edx |
| 143 | jnc sipi_complete |
| 144 | bswapl %ebx |
| 145 | movzx %bh, %edi |
| 146 | cmpb $1, %bh |
| 147 | jbe sipi_complete /* only one LAPIC ID in package */ |
| 148 | |
| 149 | movl $0, %eax |
| 150 | cpuid |
| 151 | movb $1, %bl |
| 152 | cmpl $4, %eax |
| 153 | jb cores_counted |
| 154 | movl $4, %eax |
| 155 | movl $0, %ecx |
| 156 | cpuid |
| 157 | shr $26, %eax |
| 158 | movb %al, %bl |
| 159 | inc %bl |
| 160 | |
| 161 | cores_counted: |
| 162 | movl %edi, %eax |
| 163 | divb %bl |
| 164 | cmpb $1, %al |
| 165 | jbe sipi_complete /* only LAPIC ID of a core */ |
| 166 | |
| 167 | /* For a hyper-threading processor, cache must not be disabled |
| 168 | * on an AP on the same physical package with the BSP. |
| 169 | */ |
| 170 | |
| 171 | hyper_threading_cpu: |
| 172 | |
| 173 | /* delay 10 ms */ |
| 174 | movl $10000, %ecx |
| 175 | 1: inb $0x80, %al |
| 176 | dec %ecx |
| 177 | jnz 1b |
| 178 | |
| 179 | post_code(0x25) |
| 180 | |
| 181 | /* Send Start IPI to all excluding ourself. */ |
| 182 | movl LAPIC(ICR), %edi |
| 183 | movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax |
| 184 | 1: movl %eax, (%edi) |
| 185 | movl $0x30, %ecx |
| 186 | 2: pause |
| 187 | dec %ecx |
| 188 | jnz 2b |
| 189 | movl (%edi), %ecx |
| 190 | andl $LAPIC_ICR_BUSY, %ecx |
| 191 | jnz 1b |
| 192 | |
| 193 | /* delay 250 us */ |
| 194 | movl $250, %ecx |
| 195 | 1: inb $0x80, %al |
| 196 | dec %ecx |
| 197 | jnz 1b |
| 198 | |
| 199 | post_code(0x26) |
| 200 | |
| 201 | /* Wait for sibling CPU to start. */ |
| 202 | 1: movl $(MTRR_PHYS_BASE(0)), %ecx |
| 203 | rdmsr |
| 204 | andl %eax, %eax |
| 205 | jnz sipi_complete |
| 206 | |
| 207 | movl $0x30, %ecx |
| 208 | 2: pause |
| 209 | dec %ecx |
| 210 | jnz 2b |
| 211 | jmp 1b |
| 212 | |
| 213 | |
| 214 | ap_init: |
| 215 | post_code(0x27) |
| 216 | |
| 217 | /* Do not disable cache (so BSP can enable it). */ |
| 218 | movl %cr0, %eax |
| 219 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 220 | movl %eax, %cr0 |
| 221 | |
| 222 | post_code(0x28) |
| 223 | |
| 224 | /* MTRR registers are shared between HT siblings. */ |
| 225 | movl $(MTRR_PHYS_BASE(0)), %ecx |
| 226 | movl $(1 << 12), %eax |
| 227 | xorl %edx, %edx |
| 228 | wrmsr |
| 229 | |
| 230 | post_code(0x29) |
| 231 | |
| 232 | ap_halt: |
| 233 | cli |
| 234 | 1: hlt |
| 235 | jmp 1b |
| 236 | |
| 237 | |
| 238 | |
| 239 | sipi_complete: |
| 240 | |
| 241 | post_code(0x2a) |
| 242 | |
| 243 | /* Set Cache-as-RAM base address. */ |
| 244 | movl $(MTRR_PHYS_BASE(0)), %ecx |
| 245 | movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax |
| 246 | xorl %edx, %edx |
| 247 | wrmsr |
| 248 | |
| 249 | /* Set Cache-as-RAM mask. */ |
| 250 | movl $(MTRR_PHYS_MASK(0)), %ecx |
| 251 | rdmsr |
| 252 | movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
| 253 | wrmsr |
| 254 | |
| 255 | post_code(0x2b) |
| 256 | |
| 257 | /* Enable MTRR. */ |
| 258 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 259 | rdmsr |
| 260 | orl $MTRR_DEF_TYPE_EN, %eax |
| 261 | wrmsr |
| 262 | |
| 263 | /* Enable L2 cache Write-Back (WBINVD and FLUSH#). |
| 264 | * |
| 265 | * MSR is set when DisplayFamily_DisplayModel is one of: |
| 266 | * 06_0x, 06_17, 06_1C |
| 267 | * |
| 268 | * Description says this bit enables use of WBINVD and FLUSH#. |
| 269 | * Should this be set only after the system bus and/or memory |
| 270 | * controller can successfully handle write cycles? |
| 271 | */ |
| 272 | |
| 273 | #define EAX_FAMILY(a) (a << 8) /* for family <= 0fH */ |
| 274 | #define EAX_MODEL(a) (((a & 0xf0) << 12) | ((a & 0xf) << 4)) |
| 275 | |
| 276 | movl $1, %eax |
| 277 | cpuid |
| 278 | movl %eax, %ebx |
| 279 | andl $EAX_FAMILY(0x0f), %eax |
| 280 | cmpl $EAX_FAMILY(0x06), %eax |
| 281 | jne no_msr_11e |
| 282 | movl %ebx, %eax |
| 283 | andl $EAX_MODEL(0xff), %eax |
| 284 | cmpl $EAX_MODEL(0x17), %eax |
| 285 | je has_msr_11e |
| 286 | cmpl $EAX_MODEL(0x1c), %eax |
| 287 | je has_msr_11e |
| 288 | andl $EAX_MODEL(0xf0), %eax |
| 289 | cmpl $EAX_MODEL(0x00), %eax |
| 290 | jne no_msr_11e |
| 291 | has_msr_11e: |
| 292 | movl $0x11e, %ecx |
| 293 | rdmsr |
| 294 | orl $(1 << 8), %eax |
| 295 | wrmsr |
| 296 | no_msr_11e: |
| 297 | |
| 298 | post_code(0x2c) |
| 299 | |
Arthur Heymans | 95b3ba5 | 2019-01-09 12:24:58 +0100 | [diff] [blame^] | 300 | /* Cache the whole rom to fetch microcode updates */ |
| 301 | movl $MTRR_PHYS_BASE(1), %ecx |
| 302 | xorl %edx, %edx |
| 303 | movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax |
| 304 | wrmsr |
| 305 | |
| 306 | movl $MTRR_PHYS_MASK(1), %ecx |
| 307 | rdmsr |
| 308 | movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
| 309 | wrmsr |
| 310 | |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 311 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
| 312 | movl %cr0, %eax |
| 313 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 314 | invd |
| 315 | movl %eax, %cr0 |
| 316 | |
Arthur Heymans | 95b3ba5 | 2019-01-09 12:24:58 +0100 | [diff] [blame^] | 317 | #if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM) |
| 318 | update_microcode: |
| 319 | /* put the return address in %esp */ |
| 320 | movl $end_microcode_update, %esp |
| 321 | jmp update_bsp_microcode |
| 322 | end_microcode_update: |
| 323 | #endif |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 324 | post_code(0x2d) |
Arthur Heymans | 95b3ba5 | 2019-01-09 12:24:58 +0100 | [diff] [blame^] | 325 | /* Disable caching to change MTRR's. */ |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 326 | movl %cr0, %eax |
| 327 | orl $CR0_CacheDisable, %eax |
| 328 | movl %eax, %cr0 |
| 329 | |
Arthur Heymans | 7875dbd | 2018-06-16 20:01:47 +0200 | [diff] [blame] | 330 | /* |
| 331 | * An unidentified combination of speculative reads and branch |
| 332 | * predictions inside WRPROT-cacheable memory can cause invalidation |
| 333 | * of cachelines and loss of stack on models based on NetBurst |
| 334 | * microarchitecture. Therefore disable WRPROT region entirely for |
| 335 | * all family F models. |
| 336 | */ |
| 337 | movl $1, %eax |
| 338 | cpuid |
| 339 | cmp $0xf, %ah |
Arthur Heymans | 95b3ba5 | 2019-01-09 12:24:58 +0100 | [diff] [blame^] | 340 | jne cache_rom |
Arthur Heymans | 7875dbd | 2018-06-16 20:01:47 +0200 | [diff] [blame] | 341 | |
Arthur Heymans | 95b3ba5 | 2019-01-09 12:24:58 +0100 | [diff] [blame^] | 342 | disable_cache_rom: |
| 343 | movl $MTRR_PHYS_MASK(1), %ecx |
| 344 | rdmsr |
| 345 | andl $(~MTRR_PHYS_MASK_VALID), %eax |
| 346 | wrmsr |
| 347 | jmp fill_cache |
| 348 | |
| 349 | cache_rom: |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 350 | /* Enable cache for our code in Flash because we do XIP here */ |
| 351 | movl $MTRR_PHYS_BASE(1), %ecx |
| 352 | xorl %edx, %edx |
| 353 | /* |
| 354 | * IMPORTANT: The following calculation _must_ be done at runtime. See |
Stefan Tauner | de02878 | 2018-08-19 20:02:05 +0200 | [diff] [blame] | 355 | * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 356 | */ |
Kyösti Mälkki | ce9f422 | 2018-06-25 18:53:36 +0300 | [diff] [blame] | 357 | movl $_program, %eax |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 358 | andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax |
| 359 | orl $MTRR_TYPE_WRPROT, %eax |
| 360 | wrmsr |
| 361 | |
| 362 | movl $MTRR_PHYS_MASK(1), %ecx |
| 363 | rdmsr |
| 364 | movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
| 365 | wrmsr |
| 366 | |
Arthur Heymans | 95b3ba5 | 2019-01-09 12:24:58 +0100 | [diff] [blame^] | 367 | fill_cache: |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 368 | post_code(0x2e) |
| 369 | /* Enable cache. */ |
| 370 | movl %cr0, %eax |
| 371 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Arthur Heymans | 95b3ba5 | 2019-01-09 12:24:58 +0100 | [diff] [blame^] | 372 | invd |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 373 | movl %eax, %cr0 |
| 374 | |
Arthur Heymans | 95b3ba5 | 2019-01-09 12:24:58 +0100 | [diff] [blame^] | 375 | /* Clear the cache memory region. This will also fill up the cache. */ |
| 376 | cld |
| 377 | xorl %eax, %eax |
| 378 | movl $CACHE_AS_RAM_BASE, %edi |
| 379 | movl $(CACHE_AS_RAM_SIZE >> 2), %ecx |
| 380 | rep stosl |
| 381 | |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 382 | /* Setup the stack. */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 383 | mov $_car_stack_end, %esp |
| 384 | |
| 385 | /* Need to align stack to 16 bytes at call instruction. Account for |
| 386 | the pushes below. */ |
Arthur Heymans | 348b79f | 2018-06-03 17:14:19 +0200 | [diff] [blame] | 387 | andl $0xfffffff0, %esp |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 388 | subl $4, %esp |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 389 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 390 | /* push TSC and BIST to stack */ |
| 391 | movd %mm0, %eax |
| 392 | pushl %eax /* BIST */ |
| 393 | movd %mm2, %eax |
| 394 | pushl %eax /* tsc[63:32] */ |
| 395 | movd %mm1, %eax |
| 396 | pushl %eax /* tsc[31:0] */ |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 397 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 398 | before_c_entry: |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 399 | post_code(0x2f) |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 400 | call bootblock_c_entry_bist |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 401 | |
| 402 | /* Should never see this postcode */ |
| 403 | post_code(POST_DEAD_CODE) |
| 404 | |
| 405 | .Lhlt: |
| 406 | hlt |
| 407 | jmp .Lhlt |
| 408 | |
| 409 | fixed_mtrr_list: |
| 410 | .word MTRR_FIX_64K_00000 |
| 411 | .word MTRR_FIX_16K_80000 |
| 412 | .word MTRR_FIX_16K_A0000 |
| 413 | .word MTRR_FIX_4K_C0000 |
| 414 | .word MTRR_FIX_4K_C8000 |
| 415 | .word MTRR_FIX_4K_D0000 |
| 416 | .word MTRR_FIX_4K_D8000 |
| 417 | .word MTRR_FIX_4K_E0000 |
| 418 | .word MTRR_FIX_4K_E8000 |
| 419 | .word MTRR_FIX_4K_F0000 |
| 420 | .word MTRR_FIX_4K_F8000 |
| 421 | fixed_mtrr_list_size = . - fixed_mtrr_list |
| 422 | |
| 423 | _cache_as_ram_setup_end: |