Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
| 5 | * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) |
| 6 | * Copyright (C) 2007-2008 coresystems GmbH |
| 7 | * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <cpu/x86/mtrr.h> |
| 20 | #include <cpu/x86/cache.h> |
| 21 | #include <cpu/x86/post_code.h> |
| 22 | #include <cpu/x86/lapic_def.h> |
| 23 | |
| 24 | /* Macro to access Local APIC registers at default base. */ |
| 25 | #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) |
| 26 | #define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) |
| 27 | |
| 28 | #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE |
| 29 | #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |
| 30 | |
| 31 | .code32 |
| 32 | _cache_as_ram_setup: |
| 33 | |
| 34 | /* Save the BIST result. */ |
| 35 | movl %eax, %ebp |
| 36 | |
| 37 | cache_as_ram: |
| 38 | post_code(0x20) |
| 39 | |
| 40 | movl $LAPIC_BASE_MSR, %ecx |
| 41 | rdmsr |
| 42 | andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax |
| 43 | jz ap_init |
| 44 | |
| 45 | /* Clear/disable fixed MTRRs */ |
| 46 | mov $fixed_mtrr_list_size, %ebx |
| 47 | xor %eax, %eax |
| 48 | xor %edx, %edx |
| 49 | |
| 50 | clear_fixed_mtrr: |
| 51 | add $-2, %ebx |
| 52 | movzwl fixed_mtrr_list(%ebx), %ecx |
| 53 | wrmsr |
| 54 | jnz clear_fixed_mtrr |
| 55 | |
| 56 | /* Figure put how many MTRRs we have, and clear them out */ |
| 57 | mov $MTRR_CAP_MSR, %ecx |
| 58 | rdmsr |
| 59 | movzb %al, %ebx /* Number of variable MTRRs */ |
| 60 | mov $MTRR_PHYS_BASE(0), %ecx |
| 61 | xor %eax, %eax |
| 62 | xor %edx, %edx |
| 63 | |
| 64 | clear_var_mtrr: |
| 65 | wrmsr |
| 66 | inc %ecx |
| 67 | wrmsr |
| 68 | inc %ecx |
| 69 | dec %ebx |
| 70 | jnz clear_var_mtrr |
| 71 | post_code(0x21) |
| 72 | |
| 73 | /* Configure the default memory type to uncacheable. */ |
| 74 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 75 | rdmsr |
| 76 | andl $(~0x00000cff), %eax |
| 77 | wrmsr |
| 78 | |
| 79 | post_code(0x22) |
| 80 | |
| 81 | /* Determine CPU_ADDR_BITS and load PHYSMASK high |
| 82 | * word to %edx. |
| 83 | */ |
| 84 | movl $0x80000000, %eax |
| 85 | cpuid |
| 86 | cmpl $0x80000008, %eax |
| 87 | jc addrsize_no_MSR |
| 88 | movl $0x80000008, %eax |
| 89 | cpuid |
| 90 | movb %al, %cl |
| 91 | sub $32, %cl |
| 92 | movl $1, %edx |
| 93 | shl %cl, %edx |
| 94 | subl $1, %edx |
| 95 | jmp addrsize_set_high |
| 96 | addrsize_no_MSR: |
| 97 | movl $1, %eax |
| 98 | cpuid |
| 99 | andl $(1 << 6 | 1 << 17), %edx /* PAE or PSE36 */ |
| 100 | jz addrsize_set_high |
| 101 | movl $0x0f, %edx |
| 102 | |
| 103 | /* Preload high word of address mask (in %edx) for Variable |
| 104 | * MTRRs 0 and 1 and enable local APIC at default base. |
| 105 | */ |
| 106 | addrsize_set_high: |
| 107 | xorl %eax, %eax |
| 108 | movl $MTRR_PHYS_MASK(0), %ecx |
| 109 | wrmsr |
| 110 | movl $MTRR_PHYS_MASK(1), %ecx |
| 111 | wrmsr |
| 112 | movl $LAPIC_BASE_MSR, %ecx |
| 113 | not %edx |
| 114 | movl %edx, %ebx |
| 115 | rdmsr |
| 116 | andl %ebx, %edx |
| 117 | andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax |
| 118 | orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax |
| 119 | wrmsr |
| 120 | |
| 121 | bsp_init: |
| 122 | |
| 123 | post_code(0x23) |
| 124 | |
| 125 | /* Send INIT IPI to all excluding ourself. */ |
| 126 | movl LAPIC(ICR), %edi |
| 127 | movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax |
| 128 | 1: movl %eax, (%edi) |
| 129 | movl $0x30, %ecx |
| 130 | 2: pause |
| 131 | dec %ecx |
| 132 | jnz 2b |
| 133 | movl (%edi), %ecx |
| 134 | andl $LAPIC_ICR_BUSY, %ecx |
| 135 | jnz 1b |
| 136 | |
| 137 | post_code(0x24) |
| 138 | |
| 139 | movl $1, %eax |
| 140 | cpuid |
| 141 | btl $28, %edx |
| 142 | jnc sipi_complete |
| 143 | bswapl %ebx |
| 144 | movzx %bh, %edi |
| 145 | cmpb $1, %bh |
| 146 | jbe sipi_complete /* only one LAPIC ID in package */ |
| 147 | |
| 148 | movl $0, %eax |
| 149 | cpuid |
| 150 | movb $1, %bl |
| 151 | cmpl $4, %eax |
| 152 | jb cores_counted |
| 153 | movl $4, %eax |
| 154 | movl $0, %ecx |
| 155 | cpuid |
| 156 | shr $26, %eax |
| 157 | movb %al, %bl |
| 158 | inc %bl |
| 159 | |
| 160 | cores_counted: |
| 161 | movl %edi, %eax |
| 162 | divb %bl |
| 163 | cmpb $1, %al |
| 164 | jbe sipi_complete /* only LAPIC ID of a core */ |
| 165 | |
| 166 | /* For a hyper-threading processor, cache must not be disabled |
| 167 | * on an AP on the same physical package with the BSP. |
| 168 | */ |
| 169 | |
| 170 | hyper_threading_cpu: |
| 171 | |
| 172 | /* delay 10 ms */ |
| 173 | movl $10000, %ecx |
| 174 | 1: inb $0x80, %al |
| 175 | dec %ecx |
| 176 | jnz 1b |
| 177 | |
| 178 | post_code(0x25) |
| 179 | |
| 180 | /* Send Start IPI to all excluding ourself. */ |
| 181 | movl LAPIC(ICR), %edi |
| 182 | movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax |
| 183 | 1: movl %eax, (%edi) |
| 184 | movl $0x30, %ecx |
| 185 | 2: pause |
| 186 | dec %ecx |
| 187 | jnz 2b |
| 188 | movl (%edi), %ecx |
| 189 | andl $LAPIC_ICR_BUSY, %ecx |
| 190 | jnz 1b |
| 191 | |
| 192 | /* delay 250 us */ |
| 193 | movl $250, %ecx |
| 194 | 1: inb $0x80, %al |
| 195 | dec %ecx |
| 196 | jnz 1b |
| 197 | |
| 198 | post_code(0x26) |
| 199 | |
| 200 | /* Wait for sibling CPU to start. */ |
| 201 | 1: movl $(MTRR_PHYS_BASE(0)), %ecx |
| 202 | rdmsr |
| 203 | andl %eax, %eax |
| 204 | jnz sipi_complete |
| 205 | |
| 206 | movl $0x30, %ecx |
| 207 | 2: pause |
| 208 | dec %ecx |
| 209 | jnz 2b |
| 210 | jmp 1b |
| 211 | |
| 212 | |
| 213 | ap_init: |
| 214 | post_code(0x27) |
| 215 | |
| 216 | /* Do not disable cache (so BSP can enable it). */ |
| 217 | movl %cr0, %eax |
| 218 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 219 | movl %eax, %cr0 |
| 220 | |
| 221 | post_code(0x28) |
| 222 | |
| 223 | /* MTRR registers are shared between HT siblings. */ |
| 224 | movl $(MTRR_PHYS_BASE(0)), %ecx |
| 225 | movl $(1 << 12), %eax |
| 226 | xorl %edx, %edx |
| 227 | wrmsr |
| 228 | |
| 229 | post_code(0x29) |
| 230 | |
| 231 | ap_halt: |
| 232 | cli |
| 233 | 1: hlt |
| 234 | jmp 1b |
| 235 | |
| 236 | |
| 237 | |
| 238 | sipi_complete: |
| 239 | |
| 240 | post_code(0x2a) |
| 241 | |
| 242 | /* Set Cache-as-RAM base address. */ |
| 243 | movl $(MTRR_PHYS_BASE(0)), %ecx |
| 244 | movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax |
| 245 | xorl %edx, %edx |
| 246 | wrmsr |
| 247 | |
| 248 | /* Set Cache-as-RAM mask. */ |
| 249 | movl $(MTRR_PHYS_MASK(0)), %ecx |
| 250 | rdmsr |
| 251 | movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
| 252 | wrmsr |
| 253 | |
| 254 | post_code(0x2b) |
| 255 | |
| 256 | /* Enable MTRR. */ |
| 257 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 258 | rdmsr |
| 259 | orl $MTRR_DEF_TYPE_EN, %eax |
| 260 | wrmsr |
| 261 | |
| 262 | /* Enable L2 cache Write-Back (WBINVD and FLUSH#). |
| 263 | * |
| 264 | * MSR is set when DisplayFamily_DisplayModel is one of: |
| 265 | * 06_0x, 06_17, 06_1C |
| 266 | * |
| 267 | * Description says this bit enables use of WBINVD and FLUSH#. |
| 268 | * Should this be set only after the system bus and/or memory |
| 269 | * controller can successfully handle write cycles? |
| 270 | */ |
| 271 | |
| 272 | #define EAX_FAMILY(a) (a << 8) /* for family <= 0fH */ |
| 273 | #define EAX_MODEL(a) (((a & 0xf0) << 12) | ((a & 0xf) << 4)) |
| 274 | |
| 275 | movl $1, %eax |
| 276 | cpuid |
| 277 | movl %eax, %ebx |
| 278 | andl $EAX_FAMILY(0x0f), %eax |
| 279 | cmpl $EAX_FAMILY(0x06), %eax |
| 280 | jne no_msr_11e |
| 281 | movl %ebx, %eax |
| 282 | andl $EAX_MODEL(0xff), %eax |
| 283 | cmpl $EAX_MODEL(0x17), %eax |
| 284 | je has_msr_11e |
| 285 | cmpl $EAX_MODEL(0x1c), %eax |
| 286 | je has_msr_11e |
| 287 | andl $EAX_MODEL(0xf0), %eax |
| 288 | cmpl $EAX_MODEL(0x00), %eax |
| 289 | jne no_msr_11e |
| 290 | has_msr_11e: |
| 291 | movl $0x11e, %ecx |
| 292 | rdmsr |
| 293 | orl $(1 << 8), %eax |
| 294 | wrmsr |
| 295 | no_msr_11e: |
| 296 | |
| 297 | post_code(0x2c) |
| 298 | |
| 299 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
| 300 | movl %cr0, %eax |
| 301 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 302 | invd |
| 303 | movl %eax, %cr0 |
| 304 | |
| 305 | /* Clear the cache memory region. This will also fill up the cache. */ |
| 306 | cld |
| 307 | xorl %eax, %eax |
| 308 | movl $CACHE_AS_RAM_BASE, %edi |
| 309 | movl $(CACHE_AS_RAM_SIZE >> 2), %ecx |
| 310 | rep stosl |
| 311 | |
| 312 | post_code(0x2d) |
| 313 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 314 | movl %cr0, %eax |
| 315 | orl $CR0_CacheDisable, %eax |
| 316 | movl %eax, %cr0 |
| 317 | |
| 318 | /* Enable cache for our code in Flash because we do XIP here */ |
| 319 | movl $MTRR_PHYS_BASE(1), %ecx |
| 320 | xorl %edx, %edx |
| 321 | /* |
| 322 | * IMPORTANT: The following calculation _must_ be done at runtime. See |
| 323 | * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html |
| 324 | */ |
Kyösti Mälkki | ce9f422 | 2018-06-25 18:53:36 +0300 | [diff] [blame^] | 325 | movl $_program, %eax |
Kyösti Mälkki | 6a8ce0d | 2018-05-17 17:22:51 +0300 | [diff] [blame] | 326 | andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax |
| 327 | orl $MTRR_TYPE_WRPROT, %eax |
| 328 | wrmsr |
| 329 | |
| 330 | movl $MTRR_PHYS_MASK(1), %ecx |
| 331 | rdmsr |
| 332 | movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
| 333 | wrmsr |
| 334 | |
| 335 | post_code(0x2e) |
| 336 | /* Enable cache. */ |
| 337 | movl %cr0, %eax |
| 338 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 339 | movl %eax, %cr0 |
| 340 | |
| 341 | /* Setup the stack. */ |
| 342 | movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax |
| 343 | movl %eax, %esp |
| 344 | |
| 345 | /* Restore the BIST result. */ |
| 346 | movl %ebp, %eax |
| 347 | movl %esp, %ebp |
| 348 | pushl %eax |
| 349 | |
| 350 | before_romstage: |
| 351 | post_code(0x2f) |
| 352 | /* Call romstage.c main function. */ |
| 353 | call romstage_main |
| 354 | |
| 355 | /* Should never see this postcode */ |
| 356 | post_code(POST_DEAD_CODE) |
| 357 | |
| 358 | .Lhlt: |
| 359 | hlt |
| 360 | jmp .Lhlt |
| 361 | |
| 362 | fixed_mtrr_list: |
| 363 | .word MTRR_FIX_64K_00000 |
| 364 | .word MTRR_FIX_16K_80000 |
| 365 | .word MTRR_FIX_16K_A0000 |
| 366 | .word MTRR_FIX_4K_C0000 |
| 367 | .word MTRR_FIX_4K_C8000 |
| 368 | .word MTRR_FIX_4K_D0000 |
| 369 | .word MTRR_FIX_4K_D8000 |
| 370 | .word MTRR_FIX_4K_E0000 |
| 371 | .word MTRR_FIX_4K_E8000 |
| 372 | .word MTRR_FIX_4K_F0000 |
| 373 | .word MTRR_FIX_4K_F8000 |
| 374 | fixed_mtrr_list_size = . - fixed_mtrr_list |
| 375 | |
| 376 | _cache_as_ram_setup_end: |