Angel Pons | 163030b | 2020-04-05 13:22:07 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Gabe Black | 91b30d3 | 2013-09-26 16:27:55 -0700 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Gabe Black | 91b30d3 | 2013-09-26 16:27:55 -0700 | [diff] [blame] | 4 | #include <device/device.h> |
| 5 | #include <boot/coreboot_tables.h> |
Julius Werner | eaa9c45 | 2014-09-24 15:40:49 -0700 | [diff] [blame] | 6 | #include <gpio.h> |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 7 | #include <soc/addressmap.h> |
| 8 | #include <soc/clock.h> |
Julius Werner | f0d21ff3 | 2014-10-20 13:24:14 -0700 | [diff] [blame] | 9 | #include <soc/clk_rst.h> |
Julius Werner | f0d21ff3 | 2014-10-20 13:24:14 -0700 | [diff] [blame] | 10 | #include <soc/mc.h> |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 11 | #include <soc/nvidia/tegra/i2c.h> |
Furquan Shaikh | 2296774 | 2014-08-06 09:53:55 -0700 | [diff] [blame] | 12 | #include <soc/nvidia/tegra/usb.h> |
Julius Werner | f0d21ff3 | 2014-10-20 13:24:14 -0700 | [diff] [blame] | 13 | #include <soc/pmc.h> |
| 14 | #include <soc/spi.h> |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 15 | #include <symbols.h> |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 16 | |
| 17 | static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; |
| 18 | |
| 19 | static void set_clock_sources(void) |
| 20 | { |
Gabe Black | 41c9260 | 2014-03-05 22:07:41 -0800 | [diff] [blame] | 21 | /* |
| 22 | * The max98090 codec and the temperature sensor are on I2C1. These |
| 23 | * can both run at 400 KHz, but the kernel sets the bus to 100 KHz. |
| 24 | */ |
| 25 | clock_configure_i2c_scl_freq(i2c1, PLLP, 100); |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 26 | |
| 27 | /* |
| 28 | * MMC3 and MMC4: Set base clock frequency for SD Clock to Tegra MMC's |
| 29 | * maximum speed (48MHz) so we can change SDCLK by second stage divisor |
| 30 | * in payloads, without touching base clock. |
| 31 | */ |
| 32 | clock_configure_source(sdmmc3, PLLP, 48000); |
| 33 | clock_configure_source(sdmmc4, PLLP, 48000); |
| 34 | |
Julius Werner | edf6b57 | 2013-10-25 17:49:26 -0700 | [diff] [blame] | 35 | /* External peripheral 1: audio codec (max98090) using 12MHz CLK1. |
| 36 | * Note the source id of CLK_M for EXTPERIPH1 is 3. */ |
| 37 | clock_configure_irregular_source(extperiph1, CLK_M, 12000, 3); |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 38 | |
Julius Werner | edf6b57 | 2013-10-25 17:49:26 -0700 | [diff] [blame] | 39 | /* |
Daisuke Nojiri | 14ade70 | 2014-03-26 15:04:10 -0700 | [diff] [blame] | 40 | * We need 1.5MHz. So, we use CLK_M. CLK_DIVIDER macro returns a divisor |
| 41 | * (0xe) a little bit off from the ideal value (0xd) but it's good |
| 42 | * enough for beeps. The source id of CLK_M for I2S is 6. |
Julius Werner | edf6b57 | 2013-10-25 17:49:26 -0700 | [diff] [blame] | 43 | */ |
Daisuke Nojiri | 14ade70 | 2014-03-26 15:04:10 -0700 | [diff] [blame] | 44 | clock_configure_irregular_source(i2s1, CLK_M, 1500, 6); |
Julius Werner | edf6b57 | 2013-10-25 17:49:26 -0700 | [diff] [blame] | 45 | |
| 46 | /* Note source id of PLLP for HOST1x is 4. */ |
| 47 | clock_configure_irregular_source(host1x, PLLP, 408000, 4); |
| 48 | |
| 49 | /* Use PLLD_OUT0 as clock source for disp1 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 50 | clrsetbits32(&clk_rst->clk_src_disp1, |
| 51 | CLK_SOURCE_MASK | CLK_DIVISOR_MASK, |
| 52 | 2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT); |
Julius Werner | edf6b57 | 2013-10-25 17:49:26 -0700 | [diff] [blame] | 53 | |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 54 | } |
Gabe Black | 91b30d3 | 2013-09-26 16:27:55 -0700 | [diff] [blame] | 55 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 56 | static void setup_pinmux(void) |
| 57 | { |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 58 | // I2C1 clock. |
| 59 | pinmux_set_config(PINMUX_GEN1_I2C_SCL_INDEX, |
| 60 | PINMUX_GEN1_I2C_SCL_FUNC_I2C1 | PINMUX_INPUT_ENABLE); |
| 61 | // I2C1 data. |
| 62 | pinmux_set_config(PINMUX_GEN1_I2C_SDA_INDEX, |
| 63 | PINMUX_GEN1_I2C_SDA_FUNC_I2C1 | PINMUX_INPUT_ENABLE); |
| 64 | // I2C2 clock. |
| 65 | pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX, |
Ken Chang | a859aa3 | 2014-05-22 10:54:16 +0800 | [diff] [blame] | 66 | PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE | |
| 67 | PINMUX_OPEN_DRAIN); |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 68 | // I2C2 data. |
| 69 | pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX, |
Ken Chang | a859aa3 | 2014-05-22 10:54:16 +0800 | [diff] [blame] | 70 | PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE | |
| 71 | PINMUX_OPEN_DRAIN); |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 72 | // I2C4 (DDC) clock. |
| 73 | pinmux_set_config(PINMUX_DDC_SCL_INDEX, |
| 74 | PINMUX_DDC_SCL_FUNC_I2C4 | PINMUX_INPUT_ENABLE); |
| 75 | // I2C4 (DDC) data. |
| 76 | pinmux_set_config(PINMUX_DDC_SDA_INDEX, |
| 77 | PINMUX_DDC_SDA_FUNC_I2C4 | PINMUX_INPUT_ENABLE); |
| 78 | |
| 79 | // TODO(hungte) Revice pinmux setup, make nice little SoC functions for |
| 80 | // every single logical thing instead of dumping a wall of code below. |
| 81 | uint32_t pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE, |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 82 | pin_down = PINMUX_PULL_DOWN | PINMUX_INPUT_ENABLE, |
| 83 | pin_none = PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE; |
| 84 | |
Hung-Te Lin | 6a16f69 | 2014-04-24 21:07:05 +0800 | [diff] [blame] | 85 | // MMC3 (sdcard reader) |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 86 | pinmux_set_config(PINMUX_SDMMC3_CLK_INDEX, |
| 87 | PINMUX_SDMMC3_CLK_FUNC_SDMMC3 | pin_none); |
| 88 | pinmux_set_config(PINMUX_SDMMC3_CMD_INDEX, |
| 89 | PINMUX_SDMMC3_CMD_FUNC_SDMMC3 | pin_up); |
| 90 | pinmux_set_config(PINMUX_SDMMC3_DAT0_INDEX, |
| 91 | PINMUX_SDMMC3_DAT0_FUNC_SDMMC3 | pin_up); |
| 92 | pinmux_set_config(PINMUX_SDMMC3_DAT1_INDEX, |
| 93 | PINMUX_SDMMC3_DAT1_FUNC_SDMMC3 | pin_up); |
| 94 | pinmux_set_config(PINMUX_SDMMC3_DAT2_INDEX, |
| 95 | PINMUX_SDMMC3_DAT2_FUNC_SDMMC3 | pin_up); |
| 96 | pinmux_set_config(PINMUX_SDMMC3_DAT3_INDEX, |
| 97 | PINMUX_SDMMC3_DAT3_FUNC_SDMMC3 | pin_up); |
| 98 | pinmux_set_config(PINMUX_SDMMC3_CLK_LB_IN_INDEX, |
Ken Chang | 41359bd | 2014-04-21 17:54:28 +0800 | [diff] [blame] | 99 | PINMUX_SDMMC3_CLK_LB_IN_FUNC_SDMMC3 | pin_up); |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 100 | pinmux_set_config(PINMUX_SDMMC3_CLK_LB_OUT_INDEX, |
| 101 | PINMUX_SDMMC3_CLK_LB_OUT_FUNC_SDMMC3 | pin_down); |
| 102 | |
| 103 | // MMC3 Card Detect pin. |
| 104 | gpio_input_pullup(GPIO(V2)); |
Hung-Te Lin | 6a16f69 | 2014-04-24 21:07:05 +0800 | [diff] [blame] | 105 | // Disable SD card reader power so it can be reset even on warm boot. |
| 106 | // Payloads must enable power before accessing SD card slots. |
| 107 | gpio_output(GPIO(R0), 0); |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 108 | |
Hung-Te Lin | 6a16f69 | 2014-04-24 21:07:05 +0800 | [diff] [blame] | 109 | // MMC4 (eMMC) |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 110 | pinmux_set_config(PINMUX_SDMMC4_CLK_INDEX, |
| 111 | PINMUX_SDMMC4_CLK_FUNC_SDMMC4 | pin_none); |
| 112 | pinmux_set_config(PINMUX_SDMMC4_CMD_INDEX, |
| 113 | PINMUX_SDMMC4_CMD_FUNC_SDMMC4 | pin_up); |
| 114 | pinmux_set_config(PINMUX_SDMMC4_DAT0_INDEX, |
| 115 | PINMUX_SDMMC4_DAT0_FUNC_SDMMC4 | pin_up); |
| 116 | pinmux_set_config(PINMUX_SDMMC4_DAT1_INDEX, |
| 117 | PINMUX_SDMMC4_DAT1_FUNC_SDMMC4 | pin_up); |
| 118 | pinmux_set_config(PINMUX_SDMMC4_DAT2_INDEX, |
| 119 | PINMUX_SDMMC4_DAT2_FUNC_SDMMC4 | pin_up); |
| 120 | pinmux_set_config(PINMUX_SDMMC4_DAT3_INDEX, |
| 121 | PINMUX_SDMMC4_DAT3_FUNC_SDMMC4 | pin_up); |
| 122 | pinmux_set_config(PINMUX_SDMMC4_DAT4_INDEX, |
| 123 | PINMUX_SDMMC4_DAT4_FUNC_SDMMC4 | pin_up); |
| 124 | pinmux_set_config(PINMUX_SDMMC4_DAT5_INDEX, |
| 125 | PINMUX_SDMMC4_DAT5_FUNC_SDMMC4 | pin_up); |
| 126 | pinmux_set_config(PINMUX_SDMMC4_DAT6_INDEX, |
| 127 | PINMUX_SDMMC4_DAT6_FUNC_SDMMC4 | pin_up); |
| 128 | pinmux_set_config(PINMUX_SDMMC4_DAT7_INDEX, |
| 129 | PINMUX_SDMMC4_DAT7_FUNC_SDMMC4 | pin_up); |
| 130 | |
Julius Werner | edf6b57 | 2013-10-25 17:49:26 -0700 | [diff] [blame] | 131 | /* We pull the USB VBUS signals up but keep them as inputs since the |
| 132 | * voltage source likes to drive them low on overcurrent conditions */ |
| 133 | gpio_input_pullup(GPIO(N4)); /* USB VBUS EN0 */ |
| 134 | gpio_input_pullup(GPIO(N5)); /* USB VBUS EN1 */ |
| 135 | |
| 136 | /* Clock output 1 (for external peripheral) */ |
| 137 | pinmux_set_config(PINMUX_DAP_MCLK1_INDEX, |
| 138 | PINMUX_DAP_MCLK1_FUNC_EXTPERIPH1 | PINMUX_PULL_NONE); |
| 139 | |
| 140 | /* I2S1 */ |
| 141 | pinmux_set_config(PINMUX_DAP2_DIN_INDEX, |
Ken Chang | 41359bd | 2014-04-21 17:54:28 +0800 | [diff] [blame] | 142 | PINMUX_DAP2_DIN_FUNC_I2S1 | PINMUX_INPUT_ENABLE); |
Julius Werner | edf6b57 | 2013-10-25 17:49:26 -0700 | [diff] [blame] | 143 | pinmux_set_config(PINMUX_DAP2_DOUT_INDEX, |
| 144 | PINMUX_DAP2_DOUT_FUNC_I2S1 | PINMUX_INPUT_ENABLE); |
| 145 | pinmux_set_config(PINMUX_DAP2_FS_INDEX, |
| 146 | PINMUX_DAP2_FS_FUNC_I2S1 | PINMUX_INPUT_ENABLE); |
| 147 | pinmux_set_config(PINMUX_DAP2_SCLK_INDEX, |
| 148 | PINMUX_DAP2_SCLK_FUNC_I2S1 | PINMUX_INPUT_ENABLE); |
Andrew Chew | c38c6f7 | 2014-02-10 16:33:54 -0800 | [diff] [blame] | 149 | |
| 150 | /* PWM1 */ |
| 151 | pinmux_set_config(PINMUX_GPIO_PH1_INDEX, |
| 152 | PINMUX_GPIO_PH1_FUNC_PWM1 | PINMUX_PULL_NONE); |
Ken Chang | 41359bd | 2014-04-21 17:54:28 +0800 | [diff] [blame] | 153 | |
| 154 | /* DP HPD */ |
| 155 | pinmux_set_config(PINMUX_DP_HPD_INDEX, |
| 156 | PINMUX_DP_HPD_FUNC_DP | PINMUX_INPUT_ENABLE); |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 157 | } |
| 158 | |
| 159 | static void setup_kernel_info(void) |
| 160 | { |
| 161 | // Setup required information for Linux kernel. |
| 162 | |
| 163 | // pmc.odmdata: [18:19]: console type, [15:17]: UART id. |
| 164 | // TODO(hungte) This should be done by filling BCT values, or derived |
| 165 | // from CONFIG_CONSOLE_SERIAL_UART[A-E]. Right now we simply copy the |
| 166 | // value defined in BCT. |
| 167 | struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 168 | write32(&pmc->odmdata, 0x80080000); |
Julius Werner | edf6b57 | 2013-10-25 17:49:26 -0700 | [diff] [blame] | 169 | |
| 170 | // Not strictly info, but kernel graphics driver needs this region locked down |
| 171 | struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 172 | write32(&mc->video_protect_bom, 0); |
| 173 | write32(&mc->video_protect_size_mb, 0); |
| 174 | write32(&mc->video_protect_reg_ctrl, 1); |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 175 | } |
| 176 | |
| 177 | static void setup_ec_spi(void) |
| 178 | { |
Gabe Black | 967058f | 2014-03-21 21:32:12 -0700 | [diff] [blame] | 179 | tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 180 | } |
| 181 | |
Elyes HAOUAS | d129d43 | 2018-05-04 20:23:33 +0200 | [diff] [blame] | 182 | static void mainboard_init(struct device *dev) |
Gabe Black | 91b30d3 | 2013-09-26 16:27:55 -0700 | [diff] [blame] | 183 | { |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 184 | set_clock_sources(); |
Julius Werner | edf6b57 | 2013-10-25 17:49:26 -0700 | [diff] [blame] | 185 | |
| 186 | clock_external_output(1); /* For external MAX98090 audio codec. */ |
| 187 | |
| 188 | /* |
| 189 | * Confirmed by NVIDIA hardware team, we need to take ALL audio devices |
| 190 | * conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out |
| 191 | * of reset and clock-enabled, otherwise reading AHUB devices (In our |
| 192 | * case, I2S/APBIF/AUDIO<XBAR>) will hang. |
Andrew Bresticker | 24d4f7f | 2013-12-18 22:41:34 -0800 | [diff] [blame] | 193 | * |
| 194 | * Note that CLK_H_MEM (MC) and CLK_H_EMC should be already either |
| 195 | * initialized by BootROM, or in romstage SDRAM initialization. |
Julius Werner | edf6b57 | 2013-10-25 17:49:26 -0700 | [diff] [blame] | 196 | */ |
| 197 | clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 | |
| 198 | CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 | |
| 199 | CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 | |
Andrew Chew | c38c6f7 | 2014-02-10 16:33:54 -0800 | [diff] [blame] | 200 | CLK_L_HOST1X | CLK_L_PWM, |
Julius Werner | edf6b57 | 2013-10-25 17:49:26 -0700 | [diff] [blame] | 201 | |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 202 | CLK_H_I2C2 | CLK_H_PMC | CLK_H_USB3, |
Julius Werner | edf6b57 | 2013-10-25 17:49:26 -0700 | [diff] [blame] | 203 | |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 204 | CLK_U_CSITE | CLK_U_SDMMC3, |
Julius Werner | edf6b57 | 2013-10-25 17:49:26 -0700 | [diff] [blame] | 205 | |
| 206 | CLK_V_I2C4 | CLK_V_EXTPERIPH1 | CLK_V_APBIF | |
| 207 | CLK_V_AUDIO | CLK_V_I2S3 | CLK_V_I2S4 | |
| 208 | CLK_V_DAM0 | CLK_V_DAM1 | CLK_V_DAM2, |
| 209 | |
| 210 | CLK_W_DVFS | CLK_W_AMX0 | CLK_W_ADX0, |
| 211 | |
| 212 | CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_AMX1 | |
| 213 | CLK_X_ADX1 | CLK_X_AFC0 | CLK_X_AFC1 | |
| 214 | CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 | |
| 215 | CLK_X_AFC5); |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 216 | |
Furquan Shaikh | 2296774 | 2014-08-06 09:53:55 -0700 | [diff] [blame] | 217 | usb_setup_utmip((void*)TEGRA_USBD_BASE); |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 218 | /* USB2 is the camera, we don't need it in firmware */ |
Furquan Shaikh | 2296774 | 2014-08-06 09:53:55 -0700 | [diff] [blame] | 219 | usb_setup_utmip((void*)TEGRA_USB3_BASE); |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 220 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 221 | setup_pinmux(); |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 222 | |
| 223 | i2c_init(0); |
| 224 | i2c_init(1); |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 225 | i2c_init(3); |
| 226 | |
| 227 | setup_kernel_info(); |
| 228 | clock_init_arm_generic_timer(); |
| 229 | setup_ec_spi(); |
Gabe Black | 91b30d3 | 2013-09-26 16:27:55 -0700 | [diff] [blame] | 230 | } |
| 231 | |
Elyes HAOUAS | d129d43 | 2018-05-04 20:23:33 +0200 | [diff] [blame] | 232 | static void mainboard_enable(struct device *dev) |
Gabe Black | 91b30d3 | 2013-09-26 16:27:55 -0700 | [diff] [blame] | 233 | { |
| 234 | dev->ops->init = &mainboard_init; |
| 235 | } |
| 236 | |
| 237 | struct chip_operations mainboard_ops = { |
Gabe Black | 91b30d3 | 2013-09-26 16:27:55 -0700 | [diff] [blame] | 238 | .enable_dev = mainboard_enable, |
| 239 | }; |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 240 | |
| 241 | void lb_board(struct lb_header *header) |
| 242 | { |
| 243 | struct lb_range *dma; |
| 244 | |
| 245 | dma = (struct lb_range *)lb_new_record(header); |
Patrick Georgi | 68999a8 | 2019-05-23 12:44:00 +0200 | [diff] [blame] | 246 | dma->tag = LB_TAG_DMA; |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 247 | dma->size = sizeof(*dma); |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 248 | dma->range_start = (uintptr_t)_dma_coherent; |
Julius Werner | 7e0dea6 | 2019-02-20 18:39:22 -0800 | [diff] [blame] | 249 | dma->range_size = REGION_SIZE(dma_coherent); |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 250 | } |