Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
Angel Pons | 79e3a1f | 2020-10-25 23:44:30 +0100 | [diff] [blame] | 3 | #include "../haswell.h" |
| 4 | #include <southbridge/intel/common/rcba.h> |
| 5 | |
Angel Pons | c5381e0 | 2020-10-25 12:56:29 +0100 | [diff] [blame] | 6 | Name (_HID, EISAID ("PNP0A08")) // PCIe |
| 7 | Name (_CID, EISAID ("PNP0A03")) // PCI |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 8 | |
Angel Pons | c5381e0 | 2020-10-25 12:56:29 +0100 | [diff] [blame] | 9 | Name (_BBN, 0) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 10 | |
| 11 | Device (MCHC) |
| 12 | { |
Angel Pons | c5381e0 | 2020-10-25 12:56:29 +0100 | [diff] [blame] | 13 | Name (_ADR, 0x00000000) // 0:0.0 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 14 | |
Angel Pons | c5381e0 | 2020-10-25 12:56:29 +0100 | [diff] [blame] | 15 | OperationRegion (MCHP, PCI_Config, 0x00, 0x100) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 16 | Field (MCHP, DWordAcc, NoLock, Preserve) |
| 17 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 18 | Offset (0x70), // ME Base Address |
| 19 | MEBA, 64, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 20 | Offset (0xa0), // Top of Used Memory |
| 21 | TOM, 64, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 22 | Offset (0xbc), // Top of Low Used Memory |
| 23 | TLUD, 32, |
| 24 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 25 | } |
| 26 | |
| 27 | // Current Resource Settings |
Martin Roth | fc70643 | 2015-08-18 16:56:05 -0600 | [diff] [blame] | 28 | Name (MCRS, ResourceTemplate() |
| 29 | { |
| 30 | // Bus Numbers |
| 31 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 32 | 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) |
| 33 | |
| 34 | // IO Region 0 |
| 35 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 36 | 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) |
| 37 | |
| 38 | // PCI Config Space |
| 39 | Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
| 40 | |
| 41 | // IO Region 1 |
| 42 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 43 | 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) |
| 44 | |
| 45 | // VGA memory (0xa0000-0xbffff) |
| 46 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 47 | Cacheable, ReadWrite, |
| 48 | 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
| 49 | 0x00020000,,, ASEG) |
| 50 | |
| 51 | // OPROM reserved (0xc0000-0xc3fff) |
| 52 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 53 | Cacheable, ReadWrite, |
| 54 | 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, |
| 55 | 0x00004000,,, OPR0) |
| 56 | |
| 57 | // OPROM reserved (0xc4000-0xc7fff) |
| 58 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 59 | Cacheable, ReadWrite, |
| 60 | 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, |
| 61 | 0x00004000,,, OPR1) |
| 62 | |
| 63 | // OPROM reserved (0xc8000-0xcbfff) |
| 64 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 65 | Cacheable, ReadWrite, |
| 66 | 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, |
| 67 | 0x00004000,,, OPR2) |
| 68 | |
| 69 | // OPROM reserved (0xcc000-0xcffff) |
| 70 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 71 | Cacheable, ReadWrite, |
| 72 | 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, |
| 73 | 0x00004000,,, OPR3) |
| 74 | |
| 75 | // OPROM reserved (0xd0000-0xd3fff) |
| 76 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 77 | Cacheable, ReadWrite, |
| 78 | 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, |
| 79 | 0x00004000,,, OPR4) |
| 80 | |
| 81 | // OPROM reserved (0xd4000-0xd7fff) |
| 82 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 83 | Cacheable, ReadWrite, |
| 84 | 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, |
| 85 | 0x00004000,,, OPR5) |
| 86 | |
| 87 | // OPROM reserved (0xd8000-0xdbfff) |
| 88 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 89 | Cacheable, ReadWrite, |
| 90 | 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, |
| 91 | 0x00004000,,, OPR6) |
| 92 | |
| 93 | // OPROM reserved (0xdc000-0xdffff) |
| 94 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 95 | Cacheable, ReadWrite, |
| 96 | 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, |
| 97 | 0x00004000,,, OPR7) |
| 98 | |
| 99 | // BIOS Extension (0xe0000-0xe3fff) |
| 100 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 101 | Cacheable, ReadWrite, |
| 102 | 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, |
| 103 | 0x00004000,,, ESG0) |
| 104 | |
| 105 | // BIOS Extension (0xe4000-0xe7fff) |
| 106 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 107 | Cacheable, ReadWrite, |
| 108 | 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, |
| 109 | 0x00004000,,, ESG1) |
| 110 | |
| 111 | // BIOS Extension (0xe8000-0xebfff) |
| 112 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 113 | Cacheable, ReadWrite, |
| 114 | 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, |
| 115 | 0x00004000,,, ESG2) |
| 116 | |
| 117 | // BIOS Extension (0xec000-0xeffff) |
| 118 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 119 | Cacheable, ReadWrite, |
| 120 | 0x00000000, 0x000ec000, 0x000effff, 0x00000000, |
| 121 | 0x00004000,,, ESG3) |
| 122 | |
| 123 | // System BIOS (0xf0000-0xfffff) |
| 124 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 125 | Cacheable, ReadWrite, |
| 126 | 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, |
| 127 | 0x00010000,,, FSEG) |
| 128 | |
| 129 | // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) |
| 130 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 131 | Cacheable, ReadWrite, |
| 132 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 133 | 0x00000000,,, PM01) |
| 134 | |
| 135 | // TPM Area (0xfed40000-0xfed44fff) |
| 136 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 137 | Cacheable, ReadWrite, |
| 138 | 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, |
| 139 | 0x00005000,,, TPMR) |
| 140 | }) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 141 | |
| 142 | Method (_CRS, 0, Serialized) |
| 143 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 144 | // Find PCI resource area in MCRS |
Angel Pons | c5381e0 | 2020-10-25 12:56:29 +0100 | [diff] [blame] | 145 | CreateDwordField (MCRS, ^PM01._MIN, PMIN) |
| 146 | CreateDwordField (MCRS, ^PM01._MAX, PMAX) |
| 147 | CreateDwordField (MCRS, ^PM01._LEN, PLEN) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 148 | |
| 149 | // Fix up PCI memory region |
| 150 | // Start with Top of Lower Usable DRAM |
Furquan Shaikh | 506479d | 2020-06-01 13:27:16 -0700 | [diff] [blame] | 151 | // Lower 20 bits of TOLUD register need to be masked since they contain lock and |
| 152 | // reserved bits. |
| 153 | Local0 = ^MCHC.TLUD & (0xfff << 20) |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 154 | Local1 = ^MCHC.MEBA |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 155 | |
| 156 | // Check if ME base is equal |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 157 | If (Local0 == Local1) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 158 | // Use Top Of Memory instead |
Furquan Shaikh | 506479d | 2020-06-01 13:27:16 -0700 | [diff] [blame] | 159 | // Lower 20 bits of TOM register need to be masked since they contain lock and |
| 160 | // reserved bits. |
| 161 | Local0 = ^MCHC.TOM & (0x7ffff << 20) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 162 | } |
| 163 | |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 164 | PMIN = Local0 |
| 165 | PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 |
Angel Pons | c5381e0 | 2020-10-25 12:56:29 +0100 | [diff] [blame] | 166 | PLEN = (PMAX - PMIN) + 1 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 167 | |
| 168 | Return (MCRS) |
| 169 | } |
Angel Pons | f239b5a | 2020-10-25 12:58:32 +0100 | [diff] [blame] | 170 | |
Angel Pons | 79e3a1f | 2020-10-25 23:44:30 +0100 | [diff] [blame] | 171 | /* PCI Device Resource Consumption */ |
| 172 | Device (PDRC) |
| 173 | { |
| 174 | Name (_HID, EISAID ("PNP0C02")) |
| 175 | Name (_UID, 1) |
| 176 | |
| 177 | Name (PDRS, ResourceTemplate () { |
| 178 | Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000) |
| 179 | Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) |
| 180 | Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) |
| 181 | Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) |
| 182 | Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) |
| 183 | Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH |
| 184 | Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH |
| 185 | Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH |
| 186 | |
| 187 | #if CONFIG(CHROMEOS_RAMOOPS) |
| 188 | Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, |
| 189 | CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) |
| 190 | #endif |
| 191 | }) |
| 192 | |
| 193 | // Current Resource Settings |
| 194 | Method (_CRS, 0, Serialized) |
| 195 | { |
| 196 | Return (PDRS) |
| 197 | } |
| 198 | } |
Angel Pons | 90f6a31 | 2020-10-26 00:01:13 +0100 | [diff] [blame^] | 199 | |
| 200 | /* Configurable TDP */ |
| 201 | #include "ctdp.asl" |
| 202 | |
| 203 | /* PCI Express Graphics */ |
| 204 | #include "peg.asl" |