Angel Pons | 60ec365 | 2020-04-03 01:22:13 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 2 | |
Angel Pons | d37b7d8 | 2020-07-03 23:52:34 +0200 | [diff] [blame] | 3 | #include <stdint.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 4 | #include <northbridge/intel/haswell/haswell.h> |
| 5 | #include <northbridge/intel/haswell/raminit.h> |
| 6 | #include <southbridge/intel/lynxpoint/pch.h> |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 7 | |
Angel Pons | 6e1c471 | 2020-07-03 13:05:10 +0200 | [diff] [blame] | 8 | void mainboard_config_rcba(void) |
| 9 | { |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 10 | /* |
| 11 | * GFX INTA -> PIRQA (MSI) |
| 12 | * D28IP_P1IP WLAN INTA -> PIRQB |
| 13 | * D28IP_P4IP ETH0 INTB -> PIRQC |
| 14 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 15 | * D26IP_E2P EHCI2 INTA -> PIRQE |
| 16 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 17 | * D31IP_SMIP SMBUS INTB -> PIRQG |
| 18 | * D31IP_TTIP THRT INTC -> PIRQH |
| 19 | * D27IP_ZIP HDA INTA -> PIRQG (MSI) |
| 20 | */ |
| 21 | |
| 22 | /* Device interrupt pin register (board specific) */ |
Angel Pons | 6e1c471 | 2020-07-03 13:05:10 +0200 | [diff] [blame] | 23 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 24 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 25 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 26 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 27 | RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | |
| 28 | (INTB << D28IP_P4IP); |
| 29 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 30 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 31 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 32 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 33 | |
| 34 | /* Device interrupt route registers */ |
Angel Pons | c05c2b3 | 2020-07-03 14:28:48 +0200 | [diff] [blame] | 35 | RCBA16(D31IR) = DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA); |
| 36 | RCBA16(D29IR) = DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG); |
| 37 | RCBA16(D28IR) = DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE); |
| 38 | RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB); |
| 39 | RCBA16(D26IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); |
| 40 | RCBA16(D25IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); |
| 41 | RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); |
Angel Pons | 6e1c471 | 2020-07-03 13:05:10 +0200 | [diff] [blame] | 42 | } |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 43 | |
Angel Pons | 90ae089 | 2021-03-12 17:00:52 +0100 | [diff] [blame^] | 44 | void mb_get_spd_map(struct spd_info *spdi) |
Angel Pons | d37b7d8 | 2020-07-03 23:52:34 +0200 | [diff] [blame] | 45 | { |
Angel Pons | 90ae089 | 2021-03-12 17:00:52 +0100 | [diff] [blame^] | 46 | spdi->addresses[0] = 0xa0; |
| 47 | spdi->addresses[1] = 0xa2; |
| 48 | spdi->addresses[2] = 0xa4; |
| 49 | spdi->addresses[3] = 0xa6; |
Angel Pons | d37b7d8 | 2020-07-03 23:52:34 +0200 | [diff] [blame] | 50 | } |
| 51 | |
Angel Pons | a3c6ed0 | 2021-02-11 13:59:12 +0100 | [diff] [blame] | 52 | const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { |
| 53 | /* Length, Enable, OCn#, Location */ |
| 54 | { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */ |
| 55 | USB_PORT_BACK_PANEL }, |
| 56 | { 0x0040, 1, 0, /* P1: Back USB3 port (OC0) */ |
| 57 | USB_PORT_BACK_PANEL }, |
| 58 | { 0x0040, 1, 1, /* P2: Flex Port on bottom (OC1) */ |
| 59 | USB_PORT_FLEX }, |
| 60 | { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: Dock connector */ |
| 61 | USB_PORT_DOCK }, |
| 62 | { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: Mini PCIE */ |
| 63 | USB_PORT_MINI_PCIE }, |
| 64 | { 0x0040, 1, 1, /* P5: USB eSATA header (OC1) */ |
| 65 | USB_PORT_FLEX }, |
| 66 | { 0x0040, 1, 3, /* P6: Front Header J8H2 (OC3) */ |
| 67 | USB_PORT_FRONT_PANEL }, |
| 68 | { 0x0040, 1, 3, /* P7: Front Header J8H2 (OC3) */ |
| 69 | USB_PORT_FRONT_PANEL }, |
| 70 | { 0x0040, 1, 4, /* P8: USB/LAN Jack (OC4) */ |
| 71 | USB_PORT_FRONT_PANEL }, |
| 72 | { 0x0040, 1, 4, /* P9: USB/LAN Jack (OC4) */ |
| 73 | USB_PORT_FRONT_PANEL }, |
| 74 | { 0x0040, 1, 5, /* P10: Front Header J7H3 (OC5) */ |
| 75 | USB_PORT_FRONT_PANEL }, |
| 76 | { 0x0040, 1, 5, /* P11: Front Header J7H3 (OC5) */ |
| 77 | USB_PORT_FRONT_PANEL }, |
| 78 | { 0x0040, 1, 6, /* P12: USB/DP Jack (OC6) */ |
| 79 | USB_PORT_FRONT_PANEL }, |
| 80 | { 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */ |
| 81 | USB_PORT_FRONT_PANEL }, |
| 82 | }; |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 83 | |
Angel Pons | a3c6ed0 | 2021-02-11 13:59:12 +0100 | [diff] [blame] | 84 | const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { |
| 85 | /* Enable, OCn# */ |
| 86 | { 1, 0 }, /* P1; */ |
| 87 | { 1, 0 }, /* P2; */ |
| 88 | { 1, 0 }, /* P3; */ |
| 89 | { 1, 0 }, /* P4; */ |
| 90 | { 1, 0 }, /* P6; */ |
| 91 | { 1, 0 }, /* P6; */ |
| 92 | }; |