Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
Marshall Dawson | a5f225f | 2017-08-18 10:07:07 -0600 | [diff] [blame] | 4 | #include <assert.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 5 | #include <console/console.h> |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 6 | #include <cpu/x86/msr.h> |
| 7 | #include <cpu/x86/mtrr.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 8 | #include <smp/node.h> |
| 9 | #include <bootblock_common.h> |
Richard Spiegel | 0ad74ac | 2017-12-08 16:53:29 -0700 | [diff] [blame] | 10 | #include <amdblocks/agesawrapper.h> |
| 11 | #include <amdblocks/agesawrapper_call.h> |
Michał Żygowski | 200d213 | 2019-12-06 12:07:52 +0100 | [diff] [blame] | 12 | #include <amdblocks/amd_pci_mmconf.h> |
Michał Żygowski | 5a66202 | 2019-12-02 17:02:00 +0100 | [diff] [blame] | 13 | #include <amdblocks/biosram.h> |
Felix Held | 199b10f | 2022-08-13 00:29:23 +0200 | [diff] [blame] | 14 | #include <amdblocks/iomap.h> |
Martin Roth | 8180427 | 2022-11-20 20:30:18 -0700 | [diff] [blame] | 15 | #include <amdblocks/post_codes.h> |
Marshall Dawson | f5e057c | 2017-10-12 16:10:14 -0600 | [diff] [blame] | 16 | #include <soc/pci_devs.h> |
Marshall Dawson | d85c4af | 2018-03-28 19:48:42 -0600 | [diff] [blame] | 17 | #include <soc/cpu.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 18 | #include <soc/southbridge.h> |
Aaron Durbin | 51e4c1a | 2018-01-24 17:42:51 -0700 | [diff] [blame] | 19 | #include <timestamp.h> |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 20 | #include <halt.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 21 | |
Marshall Dawson | c4be175 | 2018-05-07 09:59:10 -0600 | [diff] [blame] | 22 | #if CONFIG_PI_AGESA_TEMP_RAM_BASE < 0x100000 |
| 23 | #error "Error: CONFIG_PI_AGESA_TEMP_RAM_BASE must be >= 1MB" |
| 24 | #endif |
| 25 | #if CONFIG_PI_AGESA_CAR_HEAP_BASE < 0x100000 |
| 26 | #error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB" |
| 27 | #endif |
| 28 | |
| 29 | /* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 30 | static void amd_initmmio(void) |
| 31 | { |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 32 | msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); |
| 33 | int mtrr; |
| 34 | |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 35 | /* |
| 36 | * todo: AGESA currently writes variable MTRRs. Once that is |
| 37 | * corrected, un-hardcode this MTRR. |
Marshall Dawson | c4be175 | 2018-05-07 09:59:10 -0600 | [diff] [blame] | 38 | * |
| 39 | * Be careful not to use get_free_var_mtrr/set_var_mtrr pairs |
| 40 | * where all cores execute the path. Both cores within a compute |
| 41 | * unit share MTRRs. Programming core0 has the appearance of |
| 42 | * modifying core1 too. Using the pair again will create |
| 43 | * duplicate copies. |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 44 | */ |
Marshall Dawson | d85c4af | 2018-03-28 19:48:42 -0600 | [diff] [blame] | 45 | mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH; |
Felix Held | 199b10f | 2022-08-13 00:29:23 +0200 | [diff] [blame] | 46 | set_var_mtrr(mtrr, FLASH_BELOW_4GB_MAPPING_REGION_BASE, |
| 47 | FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT); |
Marshall Dawson | c4be175 | 2018-05-07 09:59:10 -0600 | [diff] [blame] | 48 | |
| 49 | mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_CAR_HEAP; |
| 50 | set_var_mtrr(mtrr, CONFIG_PI_AGESA_CAR_HEAP_BASE, |
| 51 | CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK); |
| 52 | |
| 53 | mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_TEMPRAM; |
| 54 | set_var_mtrr(mtrr, CONFIG_PI_AGESA_TEMP_RAM_BASE, |
| 55 | CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE); |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 56 | } |
| 57 | |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 58 | asmlinkage void bootblock_c_entry(uint64_t base_timestamp) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 59 | { |
Michał Żygowski | 200d213 | 2019-12-06 12:07:52 +0100 | [diff] [blame] | 60 | enable_pci_mmconf(); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 61 | amd_initmmio(); |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 62 | /* |
| 63 | * Call lib/bootblock.c main with BSP, shortcut for APs |
| 64 | */ |
| 65 | if (!boot_cpu()) { |
| 66 | void (*ap_romstage_entry)(void) = |
| 67 | (void (*)(void))get_ap_entry_ptr(); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 68 | |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 69 | ap_romstage_entry(); /* execution does not return */ |
| 70 | halt(); |
| 71 | } |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 72 | |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 73 | /* TSC cannot be relied upon. Override the TSC value passed in. */ |
Kyösti Mälkki | 101ef0b | 2019-08-18 06:58:42 +0300 | [diff] [blame] | 74 | bootblock_main_with_basetime(timestamp_get()); |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | void bootblock_soc_early_init(void) |
| 78 | { |
Felix Held | 8db77d7 | 2021-08-30 18:20:34 +0200 | [diff] [blame] | 79 | bootblock_fch_early_init(); |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame] | 80 | post_code(POSTCODE_BOOTBLOCK_SOC_EARLY_INIT); |
Felix Held | 8db77d7 | 2021-08-30 18:20:34 +0200 | [diff] [blame] | 81 | } |
| 82 | |
| 83 | void bootblock_soc_init(void) |
| 84 | { |
Felix Held | 91ef925 | 2021-01-12 23:44:05 +0100 | [diff] [blame] | 85 | if (CONFIG(AMD_SOC_CONSOLE_UART)) |
Marshall Dawson | a5f225f | 2017-08-18 10:07:07 -0600 | [diff] [blame] | 86 | assert(CONFIG_UART_FOR_CONSOLE >= 0 |
| 87 | && CONFIG_UART_FOR_CONSOLE <= 1); |
| 88 | |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 89 | u32 val = cpuid_eax(1); |
| 90 | printk(BIOS_DEBUG, "Family_Model: %08x\n", val); |
| 91 | |
Raul E Rangel | d820f4b8 | 2018-08-13 10:39:03 -0600 | [diff] [blame] | 92 | bootblock_fch_init(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 93 | } |