blob: 33a4d435d31222624f2a51bc5d27a0a0101e85b3 [file] [log] [blame]
Marc Jones352ca5b2021-03-18 17:01:06 -06001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <bootstate.h>
4#include <console/console.h>
5#include <console/debug.h>
Tim Chu8e4500a2022-12-16 08:45:53 +00006#include <cpu/x86/mp.h>
Marc Jones352ca5b2021-03-18 17:01:06 -06007#include <cpu/x86/smm.h>
Marc Jonesd77b97d2021-04-06 15:28:40 -06008#include <device/pci.h>
9#include <intelpch/lockdown.h>
Tim Chu8e4500a2022-12-16 08:45:53 +000010#include <soc/msr.h>
Marc Jonesd77b97d2021-04-06 15:28:40 -060011#include <soc/pci_devs.h>
Michael Niewöhner6b938662021-09-24 23:57:37 +020012#include <soc/pm.h>
Marc Jonesd77b97d2021-04-06 15:28:40 -060013#include <soc/util.h>
Tim Chu8e4500a2022-12-16 08:45:53 +000014#include <smp/spinlock.h>
Marc Jonesd77b97d2021-04-06 15:28:40 -060015
16#include "chip.h"
17
18static void lock_pam0123(void)
19{
20 const struct device *dev;
21
22 if (get_lockdown_config() != CHIPSET_LOCKDOWN_COREBOOT)
23 return;
24
25 dev = pcidev_path_on_bus(get_stack_busno(1), PCI_DEVFN(SAD_ALL_DEV, SAD_ALL_FUNC));
26 pci_or_config32(dev, SAD_ALL_PAM0123_CSR, PAM_LOCK);
27}
Marc Jones352ca5b2021-03-18 17:01:06 -060028
Tim Chu8e4500a2022-12-16 08:45:53 +000029DECLARE_SPIN_LOCK(msr_ppin_lock);
30
31static void lock_msr_ppin_ctl(void *unused)
32{
33 msr_t msr;
34
35 msr = rdmsr(MSR_PLATFORM_INFO);
36 if ((msr.lo & MSR_PPIN_CAP) == 0)
37 return;
38
39 spin_lock(&msr_ppin_lock);
40
41 msr = rdmsr(MSR_PPIN_CTL);
42 if (msr.lo & MSR_PPIN_CTL_LOCK) {
43 spin_unlock(&msr_ppin_lock);
44 return;
45 }
46
47 /* Clear enable and lock it */
48 msr.lo &= ~MSR_PPIN_CTL_ENABLE;
49 msr.lo |= MSR_PPIN_CTL_LOCK;
50 wrmsr(MSR_PPIN_CTL, msr);
51
52 spin_unlock(&msr_ppin_lock);
53}
54
Marc Jones352ca5b2021-03-18 17:01:06 -060055static void soc_finalize(void *unused)
56{
57 printk(BIOS_DEBUG, "Finalizing chipset.\n");
58
Michael Niewöhner6b938662021-09-24 23:57:37 +020059 /*
60 * Disable ACPI PM timer based on Kconfig
61 *
62 * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
63 * Disabling ACPI PM timer also switches off TCO.
64 *
65 * Note: In contrast to other platforms supporting PM timer emulation,
66 * disabling the PM timer must be done *after* FSP has run on Xeon-SP,
67 * because FSP makes use of the PM timer.
68 */
69 if (!CONFIG(USE_PM_ACPI_TIMER))
70 setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
71
Marc Jones352ca5b2021-03-18 17:01:06 -060072 apm_control(APM_CNT_FINALIZE);
Marc Jonesd77b97d2021-04-06 15:28:40 -060073 lock_pam0123();
Marc Jones352ca5b2021-03-18 17:01:06 -060074
Tim Chu8e4500a2022-12-16 08:45:53 +000075 if (CONFIG_MAX_SOCKET > 1) {
76 /* This MSR is package scope but run for all cpus for code simplicity */
77 if (mp_run_on_all_cpus(&lock_msr_ppin_ctl, NULL) != CB_SUCCESS)
78 printk(BIOS_ERR, "Lock PPIN CTL MSR failed\n");
79 } else {
80 lock_msr_ppin_ctl(NULL);
81 }
82
Marc Jones352ca5b2021-03-18 17:01:06 -060083 post_code(POST_OS_BOOT);
84}
85
86BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, soc_finalize, NULL);