Jeff Chase | 37bf996 | 2019-11-11 18:05:08 -0500 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Jeff Chase | 4b1bfe6 | 2020-01-16 16:36:20 -0500 | [diff] [blame] | 3 | # Enable Root port 7(x1) for TPU1 |
| 4 | register "PcieRpEnable[6]" = "1" |
| 5 | # Enable CLKREQ# |
| 6 | register "PcieRpClkReqSupport[6]" = "1" |
| 7 | # RP 7 uses SRCCLKREQ4# |
| 8 | register "PcieRpClkReqNumber[6]" = "4" |
| 9 | # RP 7, Enable Advanced Error Reporting |
| 10 | register "PcieRpAdvancedErrorReporting[6]" = "1" |
| 11 | # RP 7, Enable Latency Tolerance Reporting Mechanism |
| 12 | register "PcieRpLtrEnable[6]" = "1" |
| 13 | # RP 7 uses uses CLK SRC 4 |
| 14 | register "PcieRpClkSrcNumber[6]" = "4" |
| 15 | |
| 16 | # Enable Root port 8(x1) for TPU0 |
| 17 | register "PcieRpEnable[7]" = "1" |
| 18 | # Enable CLKREQ# |
| 19 | register "PcieRpClkReqSupport[7]" = "1" |
| 20 | # RP 8 uses SRCCLKREQ2# |
| 21 | register "PcieRpClkReqNumber[7]" = "2" |
| 22 | # RP 8, Enable Advanced Error Reporting |
| 23 | register "PcieRpAdvancedErrorReporting[7]" = "1" |
| 24 | # RP 8, Enable Latency Tolerance Reporting Mechanism |
| 25 | register "PcieRpLtrEnable[7]" = "1" |
| 26 | # RP 8 uses uses CLK SRC 2 |
| 27 | register "PcieRpClkSrcNumber[7]" = "2" |
| 28 | |
Jeff Chase | 37bf996 | 2019-11-11 18:05:08 -0500 | [diff] [blame] | 29 | # Enable Root port 9(x4) for i350 LAN |
| 30 | register "PcieRpEnable[8]" = "1" |
| 31 | # Disable CLKREQ# |
| 32 | register "PcieRpClkReqSupport[8]" = "0" |
| 33 | # RP 9, Enable Advanced Error Reporting |
| 34 | register "PcieRpAdvancedErrorReporting[8]" = "1" |
| 35 | # RP 9, Enable Latency Tolerance Reporting Mechanism |
| 36 | register "PcieRpLtrEnable[8]" = "1" |
| 37 | # RP 9 uses uses CLK SRC 2 |
| 38 | register "PcieRpClkSrcNumber[8]" = "2" |
| 39 | |
| 40 | # These are part of Root port 9(x4) |
| 41 | register "PcieRpEnable[9]" = "0" |
| 42 | register "PcieRpEnable[10]" = "0" |
| 43 | register "PcieRpEnable[11]" = "0" |
| 44 | |
| 45 | register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C |
| 46 | register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # HDMI |
| 47 | register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Rear |
| 48 | register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Rear |
| 49 | register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-A Rear |
| 50 | register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # HDMI Audio |
| 51 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
| 52 | register "usb2_ports[7]" = "USB2_PORT_EMPTY" # None |
| 53 | register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected) |
| 54 | |
| 55 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C |
| 56 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # HDMI |
| 57 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear |
| 58 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear |
| 59 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear |
| 60 | register "usb3_ports[5]" = "USB3_PORT_EMPTY" # None |
| 61 | |
| 62 | register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # TPU |
| 63 | register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM |
| 64 | register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # None |
| 65 | register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # HDMI |
| 66 | register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio |
| 67 | |
| 68 | register "SerialIoDevMode" = "{ |
| 69 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 70 | [PchSerialIoIndexI2C1] = PchSerialIoDisabled, |
| 71 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 72 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 73 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 74 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 75 | [PchSerialIoIndexSpi0] = PchSerialIoPci, |
| 76 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
| 77 | [PchSerialIoIndexUart0] = PchSerialIoSkipInit, |
| 78 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 79 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| 80 | }" |
| 81 | |
| 82 | device domain 0 on |
| 83 | device pci 14.0 on |
| 84 | chip drivers/usb/acpi |
| 85 | device usb 0.0 on |
| 86 | chip drivers/usb/acpi |
| 87 | register "desc" = ""USB2 HDMI In"" |
| 88 | register "type" = "UPC_TYPE_INTERNAL" |
| 89 | device usb 2.1 on end |
| 90 | end |
| 91 | chip drivers/usb/acpi |
| 92 | register "desc" = ""USB2 Type-A Rear Left"" |
| 93 | register "type" = "UPC_TYPE_A" |
| 94 | device usb 2.2 on end |
| 95 | end |
| 96 | chip drivers/usb/acpi |
| 97 | register "desc" = ""USB2 Type-A Rear Middle"" |
| 98 | register "type" = "UPC_TYPE_A" |
| 99 | device usb 2.3 on end |
| 100 | end |
| 101 | chip drivers/usb/acpi |
| 102 | register "desc" = ""USB2 Type-A Rear Right"" |
| 103 | register "type" = "UPC_TYPE_A" |
| 104 | device usb 2.4 on end |
| 105 | end |
| 106 | chip drivers/usb/acpi |
| 107 | register "desc" = ""USB2 HDMI Audio In"" |
| 108 | register "type" = "UPC_TYPE_INTERNAL" |
| 109 | device usb 2.5 on end |
| 110 | end |
| 111 | chip drivers/usb/acpi |
| 112 | register "desc" = ""USB3 HDMI Video In"" |
| 113 | register "type" = "UPC_TYPE_INTERNAL" |
| 114 | device usb 3.1 on end |
| 115 | end |
| 116 | chip drivers/usb/acpi |
| 117 | register "desc" = ""USB3 Type-A Rear Left"" |
| 118 | register "type" = "UPC_TYPE_USB3_A" |
| 119 | device usb 3.2 on end |
| 120 | end |
| 121 | chip drivers/usb/acpi |
| 122 | register "desc" = ""USB3 Type-A Rear Middle"" |
| 123 | register "type" = "UPC_TYPE_USB3_A" |
| 124 | device usb 3.3 on end |
| 125 | end |
| 126 | chip drivers/usb/acpi |
| 127 | register "desc" = ""USB3 Type-A Rear Right"" |
| 128 | register "type" = "UPC_TYPE_USB3_A" |
| 129 | device usb 3.4 on end |
| 130 | end |
| 131 | device usb 3.5 off end |
| 132 | end |
| 133 | end |
| 134 | end # USB xHCI |
| 135 | device pci 15.3 on |
| 136 | chip drivers/i2c/generic |
| 137 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 138 | register "desc" = ""Chrontel 7322"" |
| 139 | register "uid" = "1" |
Jeff Chase | 8d002f5 | 2020-03-25 22:07:00 -0400 | [diff] [blame^] | 140 | register "compat_string" = ""chrontel,ch7322"" |
Jeff Chase | 37bf996 | 2019-11-11 18:05:08 -0500 | [diff] [blame] | 141 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A18)" |
| 142 | device i2c 75 on end |
| 143 | end |
| 144 | chip drivers/i2c/generic |
| 145 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 146 | register "desc" = ""Chrontel 7322"" |
| 147 | register "uid" = "2" |
Jeff Chase | 8d002f5 | 2020-03-25 22:07:00 -0400 | [diff] [blame^] | 148 | register "compat_string" = ""chrontel,ch7322"" |
Jeff Chase | 37bf996 | 2019-11-11 18:05:08 -0500 | [diff] [blame] | 149 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A20)" |
| 150 | device i2c 76 on end |
| 151 | end |
| 152 | end # I2C #3 |
| 153 | device pci 19.1 on |
| 154 | chip drivers/i2c/generic |
| 155 | register "hid" = ""10EC5663"" |
| 156 | register "name" = ""RT53"" |
| 157 | register "desc" = ""Realtek RT5663"" |
| 158 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)" |
| 159 | device i2c 13 on end |
| 160 | end |
| 161 | end # I2C #5 |
Jeff Chase | 4b1bfe6 | 2020-01-16 16:36:20 -0500 | [diff] [blame] | 162 | device pci 1c.6 on end # PCI Express Port 7 for TPU1 |
| 163 | device pci 1c.7 on end # PCI Express Port 8 for TPU0 |
Jeff Chase | 37bf996 | 2019-11-11 18:05:08 -0500 | [diff] [blame] | 164 | device pci 1d.0 on end # PCI Express Port 9 for POE LAN |
| 165 | device pci 1d.1 off end # PCI Express Port 10 |
| 166 | device pci 1d.2 off end # PCI Express Port 11 |
| 167 | device pci 1d.3 off end # PCI Express Port 12 |
| 168 | end |
| 169 | end |