mb/google/endeavour: chrontel: fix interrupt and compat string
The devicetree declares the chrontel interrupt as GpioInt so the GPIO
needs to be configured as such instead of routing directly to APIC.
Also update the compatible string to conform to kernel standards.
BUG=b:146576073
TEST=install ch7322 driver; send commands using cec-ctl and verify
that the interrupt handler is called.
Change-Id: I737d951db135c53deb0f3cb956f0d0f275082251
Signed-off-by: Jeff Chase <jnchase@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
index 861e1b1..1d83793 100644
--- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
+++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
@@ -137,7 +137,7 @@
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "desc" = ""Chrontel 7322""
register "uid" = "1"
- register "compat_string" = ""chrontel,7322""
+ register "compat_string" = ""chrontel,ch7322""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A18)"
device i2c 75 on end
end
@@ -145,7 +145,7 @@
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "desc" = ""Chrontel 7322""
register "uid" = "2"
- register "compat_string" = ""chrontel,7322""
+ register "compat_string" = ""chrontel,ch7322""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A20)"
device i2c 76 on end
end