Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 2 | |
Angel Pons | e4156c3 | 2020-09-14 15:47:59 +0200 | [diff] [blame] | 3 | #ifndef __HASWELL_REGISTERS_MCHBAR_H__ |
| 4 | #define __HASWELL_REGISTERS_MCHBAR_H__ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 5 | |
Angel Pons | 82654b3 | 2020-10-13 21:45:45 +0200 | [diff] [blame] | 6 | /* Memory controller characteristics */ |
| 7 | #define NUM_CHANNELS 2 |
| 8 | #define NUM_SLOTS 2 |
| 9 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 10 | /* Register definitions */ |
| 11 | #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ |
Angel Pons | 6791ad2 | 2020-10-13 21:44:08 +0200 | [diff] [blame] | 12 | #define MAD_DIMM(ch) (0x5004 + (ch) * 4) |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 13 | #define MC_INIT_STATE_G 0x5030 |
| 14 | #define MRC_REVISION 0x5034 /* MRC Revision */ |
| 15 | |
| 16 | #define MC_LOCK 0x50fc /* Memory Controlller Lock register */ |
| 17 | |
| 18 | #define GFXVTBAR 0x5400 /* Base address for IGD */ |
| 19 | #define EDRAMBAR 0x5408 /* Base address for eDRAM */ |
| 20 | #define VTVC0BAR 0x5410 /* Base address for PEG, USB, SATA, etc. */ |
| 21 | #define INTRDIRCTL 0x5418 /* Interrupt Redirection Control (PAIR) */ |
| 22 | #define GDXCBAR 0x5420 /* Generic Debug eXternal Connection */ |
| 23 | |
| 24 | /* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */ |
| 25 | #define MMIO_PAVP_MSG 0x5500 |
| 26 | |
Angel Pons | 97f0d81 | 2020-10-23 10:53:31 +0200 | [diff] [blame] | 27 | #define PCU_DDR_PTM_CTL 0x5880 |
| 28 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 29 | /* Some power MSRs are also represented in MCHBAR */ |
| 30 | #define MCH_PKG_POWER_LIMIT_LO 0x59a0 |
| 31 | #define MCH_PKG_POWER_LIMIT_HI 0x59a4 |
| 32 | |
| 33 | #define MCH_DDR_POWER_LIMIT_LO 0x58e0 |
| 34 | #define MCH_DDR_POWER_LIMIT_HI 0x58e4 |
| 35 | |
| 36 | #define SSKPD 0x5d10 /* 64-bit scratchpad register */ |
| 37 | #define BIOS_RESET_CPL 0x5da8 /* 8-bit */ |
| 38 | |
| 39 | #define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ |
| 40 | #define SAPMCTL 0x5f00 |
| 41 | |
| 42 | #define HDAUDRID 0x6008 |
| 43 | #define UMAGFXCTL 0x6020 |
| 44 | #define VDMBDFBARKVM 0x6030 |
| 45 | #define VDMBDFBARPAVP 0x6034 |
| 46 | #define VTDTRKLCK 0x63fc |
| 47 | #define REQLIM 0x6800 |
| 48 | #define DMIVCLIM 0x7000 |
| 49 | #define CRDTLCK 0x77fc |
Angel Pons | 8cc39a5 | 2020-10-23 11:00:14 +0200 | [diff] [blame^] | 50 | #define MCARBLCK 0x7ffc |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 51 | |
Angel Pons | e4156c3 | 2020-09-14 15:47:59 +0200 | [diff] [blame] | 52 | #endif /* __HASWELL_REGISTERS_MCHBAR_H__ */ |