| Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #ifndef __HASWELL_MCHBAR_REGS_H__ |
| 18 | #define __HASWELL_MCHBAR_REGS_H__ |
| 19 | |
| 20 | /* Register definitions */ |
| 21 | #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ |
| 22 | #define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ |
| 23 | #define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ |
| 24 | #define MAD_DIMM_CH2 0x500c /* Address Decode Channel 2 (unused on HSW) */ |
| 25 | #define MC_INIT_STATE_G 0x5030 |
| 26 | #define MRC_REVISION 0x5034 /* MRC Revision */ |
| 27 | |
| 28 | #define MC_LOCK 0x50fc /* Memory Controlller Lock register */ |
| 29 | |
| 30 | #define GFXVTBAR 0x5400 /* Base address for IGD */ |
| 31 | #define EDRAMBAR 0x5408 /* Base address for eDRAM */ |
| 32 | #define VTVC0BAR 0x5410 /* Base address for PEG, USB, SATA, etc. */ |
| 33 | #define INTRDIRCTL 0x5418 /* Interrupt Redirection Control (PAIR) */ |
| 34 | #define GDXCBAR 0x5420 /* Generic Debug eXternal Connection */ |
| 35 | |
| 36 | /* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */ |
| 37 | #define MMIO_PAVP_MSG 0x5500 |
| 38 | |
| 39 | /* Some power MSRs are also represented in MCHBAR */ |
| 40 | #define MCH_PKG_POWER_LIMIT_LO 0x59a0 |
| 41 | #define MCH_PKG_POWER_LIMIT_HI 0x59a4 |
| 42 | |
| 43 | #define MCH_DDR_POWER_LIMIT_LO 0x58e0 |
| 44 | #define MCH_DDR_POWER_LIMIT_HI 0x58e4 |
| 45 | |
| 46 | #define SSKPD 0x5d10 /* 64-bit scratchpad register */ |
| 47 | #define BIOS_RESET_CPL 0x5da8 /* 8-bit */ |
| 48 | |
| 49 | #define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ |
| 50 | #define SAPMCTL 0x5f00 |
| 51 | |
| 52 | #define HDAUDRID 0x6008 |
| 53 | #define UMAGFXCTL 0x6020 |
| 54 | #define VDMBDFBARKVM 0x6030 |
| 55 | #define VDMBDFBARPAVP 0x6034 |
| 56 | #define VTDTRKLCK 0x63fc |
| 57 | #define REQLIM 0x6800 |
| 58 | #define DMIVCLIM 0x7000 |
| 59 | #define CRDTLCK 0x77fc |
| 60 | |
| 61 | #endif /* __HASWELL_MCHBAR_REGS_H__ */ |