Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | 1f12772 | 2019-06-04 09:46:36 +0200 | [diff] [blame] | 2 | |
Kyösti Mälkki | de64078 | 2019-12-03 07:30:26 +0200 | [diff] [blame] | 3 | #include <arch/bootblock.h> |
Arthur Heymans | 1f12772 | 2019-06-04 09:46:36 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Angel Pons | 8caa531 | 2020-06-21 18:03:59 +0200 | [diff] [blame^] | 5 | #include <southbridge/intel/common/early_spi.h> |
Arthur Heymans | 1f12772 | 2019-06-04 09:46:36 +0200 | [diff] [blame] | 6 | #include "pch.h" |
Arthur Heymans | 2882253 | 2019-10-10 15:50:04 +0200 | [diff] [blame] | 7 | #include "chip.h" |
Arthur Heymans | 1f12772 | 2019-06-04 09:46:36 +0200 | [diff] [blame] | 8 | |
Arthur Heymans | 1f12772 | 2019-06-04 09:46:36 +0200 | [diff] [blame] | 9 | static void enable_port80_on_lpc(void) |
| 10 | { |
Arthur Heymans | 2882253 | 2019-10-10 15:50:04 +0200 | [diff] [blame] | 11 | RCBA32(GCS) &= ~4; |
Arthur Heymans | 1f12772 | 2019-06-04 09:46:36 +0200 | [diff] [blame] | 12 | } |
| 13 | |
| 14 | static void set_spi_speed(void) |
| 15 | { |
| 16 | u32 fdod; |
| 17 | u8 ssfc; |
| 18 | |
| 19 | /* Observe SPI Descriptor Component Section 0 */ |
| 20 | RCBA32(0x38b0) = 0x1000; |
| 21 | |
| 22 | /* Extract the Write/Erase SPI Frequency from descriptor */ |
| 23 | fdod = RCBA32(0x38b4); |
| 24 | fdod >>= 24; |
| 25 | fdod &= 7; |
| 26 | |
| 27 | /* Set Software Sequence frequency to match */ |
| 28 | ssfc = RCBA8(0x3893); |
| 29 | ssfc &= ~7; |
| 30 | ssfc |= fdod; |
| 31 | RCBA8(0x3893) = ssfc; |
| 32 | } |
| 33 | |
Arthur Heymans | 2882253 | 2019-10-10 15:50:04 +0200 | [diff] [blame] | 34 | static void early_lpc_init(void) |
| 35 | { |
| 36 | const struct device *dev = pcidev_on_root(0x1f, 0); |
| 37 | const struct southbridge_intel_ibexpeak_config *config = NULL; |
| 38 | |
Arthur Heymans | d5e7a6d | 2019-11-20 12:17:18 +0100 | [diff] [blame] | 39 | /* |
| 40 | * Enable some common LPC IO ranges: |
| 41 | * - 0x2e/0x2f, 0x4e/0x4f often SuperIO |
| 42 | * - 0x60/0x64, 0x62/0x66 often KBC/EC |
| 43 | * - 0x3f0-0x3f5/0x3f7 FDD |
| 44 | * - 0x378-0x37f and 0x778-0x77f LPT |
| 45 | * - 0x2f8-0x2ff COMB |
| 46 | * - 0x3f8-0x3ff COMA |
| 47 | * - 0x208-0x20f GAMEH |
| 48 | * - 0x200-0x207 GAMEL |
| 49 | */ |
| 50 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN |
| 51 | | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN |
| 52 | | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN |
| 53 | | COMB_LPC_EN | COMA_LPC_EN); |
Arthur Heymans | 2882253 | 2019-10-10 15:50:04 +0200 | [diff] [blame] | 54 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); |
| 55 | |
| 56 | /* Clear PWR_FLR */ |
| 57 | pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, |
| 58 | (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); |
| 59 | |
| 60 | pci_write_config32(PCH_LPC_DEV, ETR3, |
| 61 | pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); |
| 62 | |
| 63 | /* Set up generic decode ranges */ |
| 64 | if (!dev) |
| 65 | return; |
| 66 | if (dev->chip_info) |
| 67 | config = dev->chip_info; |
| 68 | if (!config) |
| 69 | return; |
| 70 | |
| 71 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); |
| 72 | pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); |
| 73 | pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); |
| 74 | pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); |
| 75 | } |
| 76 | |
| 77 | |
| 78 | void bootblock_early_southbridge_init(void) |
Arthur Heymans | 1f12772 | 2019-06-04 09:46:36 +0200 | [diff] [blame] | 79 | { |
Angel Pons | 8caa531 | 2020-06-21 18:03:59 +0200 | [diff] [blame^] | 80 | enable_spi_prefetching_and_caching(); |
Arthur Heymans | 2882253 | 2019-10-10 15:50:04 +0200 | [diff] [blame] | 81 | |
| 82 | /* Enable RCBA */ |
| 83 | pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); |
| 84 | pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); |
| 85 | |
Arthur Heymans | 1f12772 | 2019-06-04 09:46:36 +0200 | [diff] [blame] | 86 | enable_port80_on_lpc(); |
| 87 | set_spi_speed(); |
| 88 | |
| 89 | /* Enable upper 128bytes of CMOS */ |
| 90 | RCBA32(RC) = (1 << 2); |
Arthur Heymans | 2882253 | 2019-10-10 15:50:04 +0200 | [diff] [blame] | 91 | |
| 92 | early_lpc_init(); |
Arthur Heymans | 1f12772 | 2019-06-04 09:46:36 +0200 | [diff] [blame] | 93 | } |