Arthur Heymans | 1f12772 | 2019-06-04 09:46:36 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <device/pci_ops.h> |
Arthur Heymans | 2882253 | 2019-10-10 15:50:04 +0200 | [diff] [blame^] | 17 | #include <cpu/intel/car/bootblock.h> |
Arthur Heymans | 1f12772 | 2019-06-04 09:46:36 +0200 | [diff] [blame] | 18 | #include "pch.h" |
Arthur Heymans | 2882253 | 2019-10-10 15:50:04 +0200 | [diff] [blame^] | 19 | #include "chip.h" |
Arthur Heymans | 1f12772 | 2019-06-04 09:46:36 +0200 | [diff] [blame] | 20 | |
| 21 | /* |
| 22 | * Enable Prefetching and Caching. |
| 23 | */ |
| 24 | static void enable_spi_prefetch(void) |
| 25 | { |
| 26 | u8 reg8; |
| 27 | pci_devfn_t dev = PCH_LPC_DEV; |
| 28 | |
| 29 | reg8 = pci_read_config8(dev, BIOS_CNTL); |
| 30 | reg8 &= ~(3 << 2); |
| 31 | reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ |
| 32 | pci_write_config8(dev, BIOS_CNTL, reg8); |
| 33 | } |
| 34 | |
| 35 | static void enable_port80_on_lpc(void) |
| 36 | { |
Arthur Heymans | 2882253 | 2019-10-10 15:50:04 +0200 | [diff] [blame^] | 37 | RCBA32(GCS) &= ~4; |
Arthur Heymans | 1f12772 | 2019-06-04 09:46:36 +0200 | [diff] [blame] | 38 | } |
| 39 | |
| 40 | static void set_spi_speed(void) |
| 41 | { |
| 42 | u32 fdod; |
| 43 | u8 ssfc; |
| 44 | |
| 45 | /* Observe SPI Descriptor Component Section 0 */ |
| 46 | RCBA32(0x38b0) = 0x1000; |
| 47 | |
| 48 | /* Extract the Write/Erase SPI Frequency from descriptor */ |
| 49 | fdod = RCBA32(0x38b4); |
| 50 | fdod >>= 24; |
| 51 | fdod &= 7; |
| 52 | |
| 53 | /* Set Software Sequence frequency to match */ |
| 54 | ssfc = RCBA8(0x3893); |
| 55 | ssfc &= ~7; |
| 56 | ssfc |= fdod; |
| 57 | RCBA8(0x3893) = ssfc; |
| 58 | } |
| 59 | |
Arthur Heymans | 2882253 | 2019-10-10 15:50:04 +0200 | [diff] [blame^] | 60 | static void early_lpc_init(void) |
| 61 | { |
| 62 | const struct device *dev = pcidev_on_root(0x1f, 0); |
| 63 | const struct southbridge_intel_ibexpeak_config *config = NULL; |
| 64 | |
| 65 | /* Add some default decode ranges: |
| 66 | - 0x2e/2f, 0x4e/0x4f |
| 67 | - EC/Mouse/KBC 60/64, 62/66 |
| 68 | - 0x3f8 COMA |
| 69 | If more are needed, update in mainboard_lpc_init hook |
| 70 | */ |
| 71 | pci_write_config16(PCH_LPC_DEV, LPC_EN, |
| 72 | CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | |
| 73 | COMA_LPC_EN); |
| 74 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); |
| 75 | |
| 76 | /* Clear PWR_FLR */ |
| 77 | pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, |
| 78 | (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); |
| 79 | |
| 80 | pci_write_config32(PCH_LPC_DEV, ETR3, |
| 81 | pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); |
| 82 | |
| 83 | /* Set up generic decode ranges */ |
| 84 | if (!dev) |
| 85 | return; |
| 86 | if (dev->chip_info) |
| 87 | config = dev->chip_info; |
| 88 | if (!config) |
| 89 | return; |
| 90 | |
| 91 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); |
| 92 | pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); |
| 93 | pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); |
| 94 | pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); |
| 95 | } |
| 96 | |
| 97 | |
| 98 | void bootblock_early_southbridge_init(void) |
Arthur Heymans | 1f12772 | 2019-06-04 09:46:36 +0200 | [diff] [blame] | 99 | { |
| 100 | enable_spi_prefetch(); |
Arthur Heymans | 2882253 | 2019-10-10 15:50:04 +0200 | [diff] [blame^] | 101 | |
| 102 | /* Enable RCBA */ |
| 103 | pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); |
| 104 | pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); |
| 105 | |
Arthur Heymans | 1f12772 | 2019-06-04 09:46:36 +0200 | [diff] [blame] | 106 | enable_port80_on_lpc(); |
| 107 | set_spi_speed(); |
| 108 | |
| 109 | /* Enable upper 128bytes of CMOS */ |
| 110 | RCBA32(RC) = (1 << 2); |
Arthur Heymans | 2882253 | 2019-10-10 15:50:04 +0200 | [diff] [blame^] | 111 | |
| 112 | early_lpc_init(); |
Arthur Heymans | 1f12772 | 2019-06-04 09:46:36 +0200 | [diff] [blame] | 113 | } |