Martin Roth | 3c963d9 | 2022-10-06 16:29:07 -0600 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | # TODO: Update for birman |
| 4 | |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 5 | chip soc/amd/phoenix |
Martin Roth | 3c963d9 | 2022-10-06 16:29:07 -0600 | [diff] [blame] | 6 | register "common_config.espi_config" = "{ |
| 7 | .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN, |
| 8 | .generic_io_range[0] = { |
| 9 | .base = 0x3f8, |
| 10 | .size = 8, |
| 11 | }, |
| 12 | .generic_io_range[1] = { |
| 13 | .base = 0x600, |
| 14 | .size = 256, |
| 15 | }, |
| 16 | .io_mode = ESPI_IO_MODE_QUAD, |
| 17 | .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, |
| 18 | .crc_check_enable = 1, |
| 19 | .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, |
| 20 | .periph_ch_en = 1, |
| 21 | .vw_ch_en = 1, |
| 22 | .oob_ch_en = 1, |
| 23 | .flash_ch_en = 0, |
| 24 | }" |
| 25 | |
| 26 | register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | |
| 27 | GPIO_I2C2_SCL | GPIO_I2C3_SCL" |
| 28 | |
| 29 | register "i2c[0].early_init" = "1" |
| 30 | register "i2c[1].early_init" = "1" |
| 31 | register "i2c[2].early_init" = "1" |
| 32 | register "i2c[3].early_init" = "1" |
| 33 | |
| 34 | # I2C Pad Control RX Select Configuration |
| 35 | register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" |
| 36 | register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" |
| 37 | register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" |
| 38 | register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" |
| 39 | |
| 40 | register "s0ix_enable" = "true" |
| 41 | |
| 42 | register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works |
| 43 | |
| 44 | register "usb_phy_custom" = "1" |
| 45 | register "usb_phy" = "{ |
| 46 | .Usb2PhyPort[0] = { |
| 47 | .compdistune = 0x3, |
| 48 | .pllbtune = 0x1, |
| 49 | .pllitune = 0x0, |
| 50 | .pllptune = 0xe, |
| 51 | .sqrxtune = 0x3, |
| 52 | .txfslstune = 0x3, |
| 53 | .txpreempamptune = 0x2, |
| 54 | .txpreemppulsetune = 0x0, |
| 55 | .txrisetune = 0x1, |
| 56 | .txvreftune = 0x3, |
| 57 | .txhsxvtune = 0x3, |
| 58 | .txrestune = 0x2, |
| 59 | }, |
| 60 | .Usb2PhyPort[1] = { |
| 61 | .compdistune = 0x3, |
| 62 | .pllbtune = 0x1, |
| 63 | .pllitune = 0x0, |
| 64 | .pllptune = 0xe, |
| 65 | .sqrxtune = 0x3, |
| 66 | .txfslstune = 0x3, |
| 67 | .txpreempamptune = 0x2, |
| 68 | .txpreemppulsetune = 0x0, |
| 69 | .txrisetune = 0x1, |
| 70 | .txvreftune = 0x3, |
| 71 | .txhsxvtune = 0x3, |
| 72 | .txrestune = 0x2, |
| 73 | }, |
| 74 | .Usb2PhyPort[2] = { |
| 75 | .compdistune = 0x3, |
| 76 | .pllbtune = 0x1, |
| 77 | .pllitune = 0x0, |
| 78 | .pllptune = 0xe, |
| 79 | .sqrxtune = 0x3, |
| 80 | .txfslstune = 0x3, |
| 81 | .txpreempamptune = 0x2, |
| 82 | .txpreemppulsetune = 0x0, |
| 83 | .txrisetune = 0x1, |
| 84 | .txvreftune = 0x3, |
| 85 | .txhsxvtune = 0x3, |
| 86 | .txrestune = 0x2, |
| 87 | }, |
| 88 | .Usb2PhyPort[3] = { |
| 89 | .compdistune = 0x3, |
| 90 | .pllbtune = 0x1, |
| 91 | .pllitune = 0x0, |
| 92 | .pllptune = 0xe, |
| 93 | .sqrxtune = 0x3, |
| 94 | .txfslstune = 0x3, |
| 95 | .txpreempamptune = 0x2, |
| 96 | .txpreemppulsetune = 0x0, |
| 97 | .txrisetune = 0x1, |
| 98 | .txvreftune = 0x3, |
| 99 | .txhsxvtune = 0x3, |
| 100 | .txrestune = 0x2, |
| 101 | }, |
| 102 | .Usb2PhyPort[4] = { |
| 103 | .compdistune = 0x3, |
| 104 | .pllbtune = 0x1, |
| 105 | .pllitune = 0x0, |
| 106 | .pllptune = 0xe, |
| 107 | .sqrxtune = 0x3, |
| 108 | .txfslstune = 0x3, |
| 109 | .txpreempamptune = 0x2, |
| 110 | .txpreemppulsetune = 0x0, |
| 111 | .txrisetune = 0x1, |
| 112 | .txvreftune = 0x3, |
| 113 | .txhsxvtune = 0x3, |
| 114 | .txrestune = 0x2, |
| 115 | }, |
| 116 | .Usb2PhyPort[5] = { |
| 117 | .compdistune = 0x3, |
| 118 | .pllbtune = 0x1, |
| 119 | .pllitune = 0x0, |
| 120 | .pllptune = 0xe, |
| 121 | .sqrxtune = 0x3, |
| 122 | .txfslstune = 0x3, |
| 123 | .txpreempamptune = 0x2, |
| 124 | .txpreemppulsetune = 0x0, |
| 125 | .txrisetune = 0x1, |
| 126 | .txvreftune = 0x3, |
| 127 | .txhsxvtune = 0x3, |
| 128 | .txrestune = 0x2, |
| 129 | }, |
Felix Held | 8c11907 | 2023-03-02 16:40:29 +0100 | [diff] [blame^] | 130 | .Usb2PhyPort[6] = { |
| 131 | .compdistune = 0x3, |
| 132 | .pllbtune = 0x1, |
| 133 | .pllitune = 0x0, |
| 134 | .pllptune = 0xe, |
| 135 | .sqrxtune = 0x3, |
| 136 | .txfslstune = 0x3, |
| 137 | .txpreempamptune = 0x2, |
| 138 | .txpreemppulsetune = 0x0, |
| 139 | .txrisetune = 0x1, |
| 140 | .txvreftune = 0x3, |
| 141 | .txhsxvtune = 0x3, |
| 142 | .txrestune = 0x2, |
| 143 | }, |
| 144 | .Usb2PhyPort[7] = { |
| 145 | .compdistune = 0x3, |
| 146 | .pllbtune = 0x1, |
| 147 | .pllitune = 0x0, |
| 148 | .pllptune = 0xe, |
| 149 | .sqrxtune = 0x3, |
| 150 | .txfslstune = 0x3, |
| 151 | .txpreempamptune = 0x2, |
| 152 | .txpreemppulsetune = 0x0, |
| 153 | .txrisetune = 0x1, |
| 154 | .txvreftune = 0x3, |
| 155 | .txhsxvtune = 0x3, |
| 156 | .txrestune = 0x2, |
| 157 | }, |
Martin Roth | 3c963d9 | 2022-10-06 16:29:07 -0600 | [diff] [blame] | 158 | .Usb3PhyPort[0] = { |
| 159 | .tx_term_ctrl = 0x2, |
| 160 | .rx_term_ctrl = 0x2, |
| 161 | .tx_vboost_lvl_en = 0x0, |
| 162 | .tx_vboost_lvl = 0x5, |
| 163 | }, |
| 164 | .Usb3PhyPort[1] = { |
| 165 | .tx_term_ctrl = 0x2, |
| 166 | .rx_term_ctrl = 0x2, |
| 167 | .tx_vboost_lvl_en = 0x0, |
| 168 | .tx_vboost_lvl = 0x5, |
| 169 | }, |
| 170 | .Usb3PhyPort[2] = { |
| 171 | .tx_term_ctrl = 0x2, |
| 172 | .rx_term_ctrl = 0x2, |
| 173 | .tx_vboost_lvl_en = 0x0, |
| 174 | .tx_vboost_lvl = 0x5, |
| 175 | }, |
| 176 | .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C, |
| 177 | .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C, |
Felix Held | 8c11907 | 2023-03-02 16:40:29 +0100 | [diff] [blame^] | 178 | .ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C, |
Martin Roth | 3c963d9 | 2022-10-06 16:29:07 -0600 | [diff] [blame] | 179 | .BatteryChargerEnable = 0, |
| 180 | .PhyP3CpmP4Support = 0, |
| 181 | }" |
| 182 | |
Fred Reitberger | c706880 | 2022-11-16 13:15:43 -0500 | [diff] [blame] | 183 | register "gpp_clk_config[0]" = "GPP_CLK_REQ" # MXM |
| 184 | register "gpp_clk_config[1]" = "GPP_CLK_REQ" # NVMe SSD1 |
| 185 | register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVMe SSD0 |
| 186 | register "gpp_clk_config[3]" = "GPP_CLK_REQ" # WLAN |
| 187 | register "gpp_clk_config[4]" = "GPP_CLK_REQ" # WWAN |
| 188 | register "gpp_clk_config[5]" = "GPP_CLK_REQ" # SD |
| 189 | register "gpp_clk_config[6]" = "GPP_CLK_REQ" # GBE |
Martin Roth | 3c963d9 | 2022-10-06 16:29:07 -0600 | [diff] [blame] | 190 | |
| 191 | device domain 0 on |
| 192 | device ref iommu on end |
Fred Reitberger | c706880 | 2022-11-16 13:15:43 -0500 | [diff] [blame] | 193 | device ref gpp_bridge_1_1 on end # MXM |
Fred Reitberger | 67bc6ab | 2023-04-06 10:01:23 -0400 | [diff] [blame] | 194 | device ref gpp_bridge_1_2 on |
| 195 | # Required so the NVMe gets placed into D3 when entering S0i3. |
| 196 | chip drivers/pcie/rtd3/device |
| 197 | register "name" = ""NVME"" |
| 198 | device pci 00.0 on end |
| 199 | end |
| 200 | end # NVMe SSD1 |
Fred Reitberger | c706880 | 2022-11-16 13:15:43 -0500 | [diff] [blame] | 201 | device ref gpp_bridge_1_3 on end # GBE |
| 202 | device ref gpp_bridge_2_1 on end # SD |
| 203 | device ref gpp_bridge_2_2 on end # WWAN |
| 204 | device ref gpp_bridge_2_3 on end # WIFI |
Fred Reitberger | 67bc6ab | 2023-04-06 10:01:23 -0400 | [diff] [blame] | 205 | device ref gpp_bridge_2_4 on |
| 206 | # Required so the NVMe gets placed into D3 when entering S0i3. |
| 207 | chip drivers/pcie/rtd3/device |
| 208 | register "name" = ""NVME"" |
| 209 | device pci 00.0 on end |
| 210 | end |
| 211 | end # NVMe SSD0 |
Martin Roth | 3c963d9 | 2022-10-06 16:29:07 -0600 | [diff] [blame] | 212 | device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A |
| 213 | device ref gfx on end # Internal GPU (GFX) |
| 214 | device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) |
| 215 | device ref crypto on end # Crypto Coprocessor |
| 216 | device ref xhci_0 on # USB 3.1 (USB0) |
| 217 | chip drivers/usb/acpi |
| 218 | device ref xhci_0_root_hub on |
| 219 | chip drivers/usb/acpi |
| 220 | device ref usb3_port0 on end |
| 221 | end |
| 222 | chip drivers/usb/acpi |
Felix Held | c489a40 | 2023-02-03 18:02:24 +0100 | [diff] [blame] | 223 | device ref usb3_port1 on end |
| 224 | end |
| 225 | chip drivers/usb/acpi |
Martin Roth | 3c963d9 | 2022-10-06 16:29:07 -0600 | [diff] [blame] | 226 | device ref usb2_port0 on end |
| 227 | end |
| 228 | chip drivers/usb/acpi |
| 229 | device ref usb2_port1 on end |
| 230 | end |
Martin Roth | 3c963d9 | 2022-10-06 16:29:07 -0600 | [diff] [blame] | 231 | chip drivers/usb/acpi |
| 232 | device ref usb2_port2 on end |
| 233 | end |
| 234 | chip drivers/usb/acpi |
| 235 | device ref usb2_port3 on end |
| 236 | end |
| 237 | chip drivers/usb/acpi |
| 238 | device ref usb2_port4 on end |
| 239 | end |
| 240 | end |
| 241 | end |
| 242 | end |
Felix Held | c489a40 | 2023-02-03 18:02:24 +0100 | [diff] [blame] | 243 | device ref xhci_1 on # USB 3.1 (USB1) |
| 244 | chip drivers/usb/acpi |
| 245 | device ref xhci_1_root_hub on |
| 246 | chip drivers/usb/acpi |
| 247 | device ref usb3_port5 on end |
| 248 | end |
| 249 | chip drivers/usb/acpi |
| 250 | device ref usb2_port5 on end |
| 251 | end |
| 252 | end |
| 253 | end |
| 254 | end |
Martin Roth | 3c963d9 | 2022-10-06 16:29:07 -0600 | [diff] [blame] | 255 | device ref acp on end # Audio Processor (ACP) |
| 256 | end |
| 257 | device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C |
Martin Roth | 3c963d9 | 2022-10-06 16:29:07 -0600 | [diff] [blame] | 258 | end |
| 259 | end |
| 260 | |
| 261 | device ref i2c_0 on end |
| 262 | device ref i2c_1 on end |
| 263 | device ref i2c_2 on end |
| 264 | device ref i2c_3 on end |
| 265 | device ref uart_0 on end # UART0 |
| 266 | |
| 267 | end |