Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | 5474eb1 | 2018-05-26 19:22:33 -0600 | [diff] [blame] | 2 | |
Kyösti Mälkki | de64078 | 2019-12-03 07:30:26 +0200 | [diff] [blame] | 3 | #include <arch/bootblock.h> |
Angel Pons | 32770f8 | 2021-01-20 15:03:30 +0100 | [diff] [blame] | 4 | #include <assert.h> |
Angel Pons | 37cae54 | 2021-02-02 16:28:07 +0100 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Angel Pons | 32770f8 | 2021-01-20 15:03:30 +0100 | [diff] [blame] | 6 | #include <types.h> |
Elyes HAOUAS | b96c358 | 2021-01-31 08:27:35 +0100 | [diff] [blame] | 7 | |
Arthur Heymans | 8e646e7 | 2018-06-05 11:19:22 +0200 | [diff] [blame] | 8 | #include "haswell.h" |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 9 | |
Angel Pons | 32770f8 | 2021-01-20 15:03:30 +0100 | [diff] [blame] | 10 | static uint32_t encode_pciexbar_length(void) |
| 11 | { |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 12 | switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { |
Angel Pons | 32770f8 | 2021-01-20 15:03:30 +0100 | [diff] [blame] | 13 | case 256: return 0 << 1; |
| 14 | case 128: return 1 << 1; |
| 15 | case 64: return 2 << 1; |
| 16 | default: return dead_code_t(uint32_t); |
| 17 | } |
| 18 | } |
| 19 | |
Arthur Heymans | 8e646e7 | 2018-06-05 11:19:22 +0200 | [diff] [blame] | 20 | void bootblock_early_northbridge_init(void) |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 21 | { |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 22 | /* |
Angel Pons | 32770f8 | 2021-01-20 15:03:30 +0100 | [diff] [blame] | 23 | * The "io" variant of the config access is explicitly used to setup the |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 24 | * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all |
Angel Pons | 32770f8 | 2021-01-20 15:03:30 +0100 | [diff] [blame] | 25 | * subsequent non-explicit config accesses use MCFG. This code also assumes |
| 26 | * that bootblock_northbridge_init() is the first thing called in the non-asm |
| 27 | * boot block code. The final assumption is that no assembly code is using the |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 28 | * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses. |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 29 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 30 | * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 31 | */ |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 32 | const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; |
Angel Pons | 32770f8 | 2021-01-20 15:03:30 +0100 | [diff] [blame] | 33 | pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); |
Elyes HAOUAS | b96c358 | 2021-01-31 08:27:35 +0100 | [diff] [blame] | 34 | pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 35 | } |