Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 4 | #include <cf9_reset.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 5 | #include <string.h> |
Keith Hui | 1e9601c | 2023-07-15 12:08:51 -0400 | [diff] [blame] | 6 | #include <cbfs.h> |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 7 | #include <arch/cpu.h> |
Keith Hui | 1e9601c | 2023-07-15 12:08:51 -0400 | [diff] [blame] | 8 | #include <device/device.h> |
| 9 | #include <device/dram/ddr3.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 10 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 11 | #include <device/pci_ops.h> |
Kyösti Mälkki | 1cae454 | 2020-01-06 12:31:34 +0200 | [diff] [blame] | 12 | #include <device/smbus_host.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 13 | #include <cbmem.h> |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 14 | #include <timestamp.h> |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 15 | #include <mrc_cache.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 16 | #include <southbridge/intel/bd82x6x/me.h> |
Patrick Rudolph | da9302a | 2019-03-24 17:01:41 +0100 | [diff] [blame] | 17 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 18 | #include <cpu/x86/msr.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 19 | #include <types.h> |
Elyes HAOUAS | bf0970e | 2019-03-21 11:10:03 +0100 | [diff] [blame] | 20 | |
Keith Hui | 1e9601c | 2023-07-15 12:08:51 -0400 | [diff] [blame] | 21 | #include "raminit.h" |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 22 | #include "raminit_common.h" |
| 23 | #include "sandybridge.h" |
Keith Hui | 1e9601c | 2023-07-15 12:08:51 -0400 | [diff] [blame] | 24 | #include "chip.h" |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 25 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 26 | /* FIXME: no support for 3-channel chipsets */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 27 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 28 | static void wait_txt_clear(void) |
| 29 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 30 | struct cpuid_result cp = cpuid_ext(1, 0); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 31 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 32 | /* Check if TXT is supported */ |
| 33 | if (!(cp.ecx & (1 << 6))) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 34 | return; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 35 | |
| 36 | /* Some TXT public bit */ |
Elyes Haouas | 4b7d405 | 2022-12-03 13:24:03 +0100 | [diff] [blame] | 37 | if (!(read32p(0xfed30010) & 1)) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 38 | return; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 39 | |
| 40 | /* Wait for TXT clear */ |
Elyes Haouas | 4b7d405 | 2022-12-03 13:24:03 +0100 | [diff] [blame] | 41 | while (!(read8p(0xfed40000) & (1 << 7))) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 42 | ; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 43 | } |
| 44 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 45 | /* Disable a channel in ramctr_timing */ |
| 46 | static void disable_channel(ramctr_timing *ctrl, int channel) |
| 47 | { |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 48 | ctrl->rankmap[channel] = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 49 | |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 50 | memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 51 | |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 52 | ctrl->channel_size_mb[channel] = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 53 | ctrl->cmd_stretch[channel] = 0; |
| 54 | ctrl->mad_dimm[channel] = 0; |
| 55 | memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); |
Patrick Rudolph | 74163d6 | 2016-11-17 20:02:43 +0100 | [diff] [blame] | 56 | memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0])); |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 57 | } |
| 58 | |
Angel Pons | 6724ba4 | 2021-01-31 15:06:59 +0100 | [diff] [blame] | 59 | static uint8_t nb_get_ecc_type(const uint32_t capid0_a) |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 60 | { |
Angel Pons | 6724ba4 | 2021-01-31 15:06:59 +0100 | [diff] [blame] | 61 | return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 62 | } |
| 63 | |
| 64 | static uint16_t nb_slots_per_channel(const uint32_t capid0_a) |
| 65 | { |
| 66 | return !(capid0_a & CAPID_DDPCD) + 1; |
| 67 | } |
| 68 | |
| 69 | static uint16_t nb_number_of_channels(const uint32_t capid0_a) |
| 70 | { |
| 71 | return !(capid0_a & CAPID_PDCD) + 1; |
| 72 | } |
| 73 | |
| 74 | static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a) |
| 75 | { |
| 76 | uint32_t ddrsz; |
| 77 | |
| 78 | /* Values from documentation, which assume two DIMMs per channel */ |
| 79 | switch (CAPID_DDRSZ(capid0_a)) { |
| 80 | case 1: |
| 81 | ddrsz = 8192; |
| 82 | break; |
| 83 | case 2: |
| 84 | ddrsz = 2048; |
| 85 | break; |
| 86 | case 3: |
| 87 | ddrsz = 512; |
| 88 | break; |
| 89 | default: |
| 90 | ddrsz = 16384; |
| 91 | break; |
| 92 | } |
| 93 | |
| 94 | /* Account for the maximum number of DIMMs per channel */ |
| 95 | return (ddrsz / 2) * nb_slots_per_channel(capid0_a); |
| 96 | } |
| 97 | |
| 98 | /* Fill cbmem with information for SMBIOS type 16 and type 17 */ |
| 99 | static void setup_sdram_meminfo(ramctr_timing *ctrl) |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 100 | { |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 101 | int channel, slot; |
Patrick Rudolph | 24efe73 | 2018-08-19 11:06:06 +0200 | [diff] [blame] | 102 | const u16 ddr_freq = (1000 << 8) / ctrl->tCK; |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 103 | |
Elyes HAOUAS | 12df950 | 2016-08-23 21:29:48 +0200 | [diff] [blame] | 104 | FOR_ALL_CHANNELS for (slot = 0; slot < NUM_SLOTS; slot++) { |
Patrick Rudolph | 24efe73 | 2018-08-19 11:06:06 +0200 | [diff] [blame] | 105 | enum cb_err ret = spd_add_smbios17(channel, slot, ddr_freq, |
| 106 | &ctrl->info.dimm[channel][slot]); |
| 107 | if (ret != CB_SUCCESS) |
| 108 | printk(BIOS_ERR, "RAMINIT: Failed to add SMBIOS17\n"); |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 109 | } |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 110 | |
| 111 | /* The 'spd_add_smbios17' function allocates this CBMEM area */ |
| 112 | struct memory_info *m = cbmem_find(CBMEM_ID_MEMINFO); |
Elyes Haouas | 5e6b0f0 | 2022-09-13 09:55:49 +0200 | [diff] [blame] | 113 | if (!m) |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 114 | return; |
| 115 | |
| 116 | const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 117 | |
| 118 | const uint16_t channels = nb_number_of_channels(capid0_a); |
| 119 | |
Angel Pons | 6724ba4 | 2021-01-31 15:06:59 +0100 | [diff] [blame] | 120 | m->ecc_type = nb_get_ecc_type(capid0_a); |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 121 | m->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); |
| 122 | m->number_of_devices = channels * nb_slots_per_channel(capid0_a); |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 123 | } |
| 124 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 125 | /* Return CRC16 match for all SPDs */ |
Elyes Haouas | 78ba7a7 | 2024-05-06 05:11:28 +0200 | [diff] [blame] | 126 | static int verify_crc16_spds_ddr3(spd_ddr3_raw_data *spd, ramctr_timing *ctrl) |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 127 | { |
| 128 | int channel, slot, spd_slot; |
| 129 | int match = 1; |
| 130 | |
| 131 | FOR_ALL_CHANNELS { |
| 132 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
| 133 | spd_slot = 2 * channel + slot; |
| 134 | match &= ctrl->spd_crc[channel][slot] == |
Elyes Haouas | 78ba7a7 | 2024-05-06 05:11:28 +0200 | [diff] [blame] | 135 | spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_ddr3_raw_data)); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 136 | } |
| 137 | } |
| 138 | return match; |
| 139 | } |
| 140 | |
Elyes Haouas | 78ba7a7 | 2024-05-06 05:11:28 +0200 | [diff] [blame] | 141 | static void read_spd(spd_ddr3_raw_data *spd, u8 addr, bool id_only) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 142 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 143 | int j; |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 144 | if (id_only) { |
Keith Hui | 1e9601c | 2023-07-15 12:08:51 -0400 | [diff] [blame] | 145 | for (j = SPD_DIMM_MOD_ID1; j < 128; j++) |
Kyösti Mälkki | 1a1b04e | 2020-01-07 22:34:33 +0200 | [diff] [blame] | 146 | (*spd)[j] = smbus_read_byte(addr, j); |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 147 | } else { |
Keith Hui | 1e9601c | 2023-07-15 12:08:51 -0400 | [diff] [blame] | 148 | for (j = 0; j < SPD_SIZE_MAX_DDR3; j++) |
Kyösti Mälkki | 1a1b04e | 2020-01-07 22:34:33 +0200 | [diff] [blame] | 149 | (*spd)[j] = smbus_read_byte(addr, j); |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 150 | } |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 151 | } |
| 152 | |
Elyes Haouas | 78ba7a7 | 2024-05-06 05:11:28 +0200 | [diff] [blame] | 153 | static void mainboard_get_spd(spd_ddr3_raw_data *spd, bool id_only) |
Keith Hui | 1e9601c | 2023-07-15 12:08:51 -0400 | [diff] [blame] | 154 | { |
| 155 | const struct northbridge_intel_sandybridge_config *cfg = config_of_soc(); |
| 156 | unsigned int i; |
| 157 | |
| 158 | if (CONFIG(HAVE_SPD_IN_CBFS)) { |
| 159 | struct spd_info spdi = {0}; |
| 160 | |
| 161 | mb_get_spd_map(&spdi); |
| 162 | |
| 163 | size_t spd_file_len; |
| 164 | uint8_t *spd_file = cbfs_map("spd.bin", &spd_file_len); |
| 165 | |
| 166 | printk(BIOS_DEBUG, "SPD index %d\n", spdi.spd_index); |
| 167 | |
| 168 | /* SPD file sanity check */ |
| 169 | if (!spd_file) |
| 170 | die("SPD data %s!", "not found"); |
| 171 | |
| 172 | if (spd_file_len < ((spdi.spd_index + 1) * SPD_SIZE_MAX_DDR3)) |
| 173 | die("SPD data %s!", "incomplete"); |
| 174 | |
| 175 | /* |
| 176 | * Copy SPD data specified by spd_info.spd_index to all slots marked as |
| 177 | * SPD_MEMORY_DOWN. |
| 178 | * |
| 179 | * Read SPD data from slots with a real SMBus address. |
| 180 | */ |
| 181 | for (i = 0; i < ARRAY_SIZE(spdi.addresses); i++) { |
| 182 | if (spdi.addresses[i] == SPD_MEMORY_DOWN) |
| 183 | memcpy(&spd[i], spd_file + (spdi.spd_index * SPD_SIZE_MAX_DDR3), SPD_SIZE_MAX_DDR3); |
| 184 | else if (spdi.addresses[i] != 0) |
| 185 | read_spd(&spd[i], spdi.addresses[i], id_only); |
| 186 | } |
| 187 | } else { |
| 188 | for (i = 0; i < ARRAY_SIZE(cfg->spd_addresses); i++) { |
| 189 | if (cfg->spd_addresses[i] != 0) |
| 190 | read_spd(&spd[i], cfg->spd_addresses[i], id_only); |
| 191 | } |
| 192 | } /* CONFIG(HAVE_SPD_IN_CBFS) */ |
| 193 | } |
| 194 | |
Elyes Haouas | 78ba7a7 | 2024-05-06 05:11:28 +0200 | [diff] [blame] | 195 | static void dram_find_spds_ddr3(spd_ddr3_raw_data *spd, ramctr_timing *ctrl) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 196 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 197 | int dimms = 0, ch_dimms; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 198 | int channel, slot, spd_slot; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 199 | bool can_use_ecc = ctrl->ecc_supported; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 200 | |
Elyes Haouas | 9d450b2 | 2023-09-10 10:30:29 +0200 | [diff] [blame] | 201 | memset(ctrl->rankmap, 0, sizeof(ctrl->rankmap)); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 202 | |
| 203 | ctrl->extended_temperature_range = 1; |
| 204 | ctrl->auto_self_refresh = 1; |
| 205 | |
| 206 | FOR_ALL_CHANNELS { |
| 207 | ctrl->channel_size_mb[channel] = 0; |
| 208 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 209 | ch_dimms = 0; |
| 210 | /* Count dimms on channel */ |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 211 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
| 212 | spd_slot = 2 * channel + slot; |
Patrick Rudolph | 5a06185 | 2017-09-22 15:19:26 +0200 | [diff] [blame] | 213 | |
Angel Pons | 035096c | 2020-09-17 22:31:19 +0200 | [diff] [blame] | 214 | if (spd[spd_slot][SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 215 | ch_dimms++; |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 216 | } |
| 217 | |
| 218 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
| 219 | spd_slot = 2 * channel + slot; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 220 | printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot); |
Patrick Rudolph | 5a06185 | 2017-09-22 15:19:26 +0200 | [diff] [blame] | 221 | |
Angel Pons | afb3d7e | 2021-03-28 13:43:13 +0200 | [diff] [blame] | 222 | struct dimm_attr_ddr3_st *const dimm = &ctrl->info.dimm[channel][slot]; |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 223 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 224 | /* Search for XMP profile */ |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 225 | spd_xmp_decode_ddr3(dimm, spd[spd_slot], |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 226 | DDR3_XMP_PROFILE_1); |
| 227 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 228 | if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 229 | printram("No valid XMP profile found.\n"); |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 230 | spd_decode_ddr3(dimm, spd[spd_slot]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 231 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 232 | } else if (ch_dimms > dimm->dimms_per_channel) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 233 | printram( |
| 234 | "XMP profile supports %u DIMMs, but %u DIMMs are installed.\n", |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 235 | dimm->dimms_per_channel, ch_dimms); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 236 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 237 | if (CONFIG(NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS)) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 238 | printk(BIOS_WARNING, |
| 239 | "XMP maximum DIMMs will be ignored.\n"); |
Vagiz Trakhanov | 771be48 | 2017-10-02 10:02:35 +0000 | [diff] [blame] | 240 | else |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 241 | spd_decode_ddr3(dimm, spd[spd_slot]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 242 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 243 | } else if (dimm->voltage != 1500) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 244 | /* TODO: Support DDR3 voltages other than 1500mV */ |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 245 | printram("XMP profile's requested %u mV is unsupported.\n", |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 246 | dimm->voltage); |
Angel Pons | 3170e9c | 2020-12-12 16:22:18 +0100 | [diff] [blame] | 247 | |
| 248 | if (CONFIG(NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE)) |
| 249 | printk(BIOS_WARNING, |
| 250 | "XMP requested voltage will be ignored.\n"); |
| 251 | else |
| 252 | spd_decode_ddr3(dimm, spd[spd_slot]); |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 253 | } |
| 254 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 255 | /* Fill in CRC16 for MRC cache */ |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 256 | ctrl->spd_crc[channel][slot] = |
Elyes Haouas | 78ba7a7 | 2024-05-06 05:11:28 +0200 | [diff] [blame] | 257 | spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_ddr3_raw_data)); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 258 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 259 | if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 260 | /* Mark DIMM as invalid */ |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 261 | dimm->ranks = 0; |
| 262 | dimm->size_mb = 0; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 263 | continue; |
| 264 | } |
| 265 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 266 | dram_print_spd_ddr3(dimm); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 267 | dimms++; |
| 268 | ctrl->rank_mirror[channel][slot * 2] = 0; |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 269 | ctrl->rank_mirror[channel][slot * 2 + 1] = dimm->flags.pins_mirrored; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 270 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 271 | ctrl->channel_size_mb[channel] += dimm->size_mb; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 272 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 273 | if (!dimm->flags.is_ecc) |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 274 | can_use_ecc = false; |
| 275 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 276 | ctrl->auto_self_refresh &= dimm->flags.asr; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 277 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 278 | ctrl->extended_temperature_range &= dimm->flags.ext_temp_refresh; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 279 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame] | 280 | ctrl->rankmap[channel] |= ((1 << dimm->ranks) - 1) << (2 * slot); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 281 | |
| 282 | printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", channel, |
| 283 | ctrl->rankmap[channel]); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 284 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 285 | |
Angel Pons | d4d3ba0 | 2020-12-12 17:45:14 +0100 | [diff] [blame] | 286 | const u8 rc_0 = ctrl->info.dimm[channel][0].reference_card; |
| 287 | const u8 rc_1 = ctrl->info.dimm[channel][1].reference_card; |
| 288 | |
| 289 | if (ch_dimms == NUM_SLOTS && rc_0 < 6 && rc_1 < 6) { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 290 | const int ref_card_offset_table[6][6] = { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 291 | { 0, 0, 0, 0, 2, 2 }, |
| 292 | { 0, 0, 0, 0, 2, 2 }, |
| 293 | { 0, 0, 0, 0, 2, 2 }, |
| 294 | { 0, 0, 0, 0, 1, 1 }, |
| 295 | { 2, 2, 2, 1, 0, 0 }, |
| 296 | { 2, 2, 2, 1, 0, 0 }, |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 297 | }; |
Angel Pons | d4d3ba0 | 2020-12-12 17:45:14 +0100 | [diff] [blame] | 298 | ctrl->ref_card_offset[channel] = ref_card_offset_table[rc_0][rc_1]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 299 | } else { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 300 | ctrl->ref_card_offset[channel] = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 301 | } |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 302 | } |
| 303 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 304 | if (ctrl->ecc_forced || CONFIG(RAMINIT_ENABLE_ECC)) |
| 305 | ctrl->ecc_enabled = can_use_ecc; |
| 306 | if (ctrl->ecc_forced && !ctrl->ecc_enabled) |
| 307 | die("ECC mode forced but non-ECC DIMM installed!"); |
| 308 | printk(BIOS_DEBUG, "ECC is %s\n", ctrl->ecc_enabled ? "enabled" : "disabled"); |
| 309 | |
| 310 | ctrl->lanes = ctrl->ecc_enabled ? 9 : 8; |
| 311 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 312 | if (!dimms) |
| 313 | die("No DIMMs were found"); |
| 314 | } |
| 315 | |
Patrick Rudolph | bb9c90a | 2016-05-29 17:05:06 +0200 | [diff] [blame] | 316 | static void save_timings(ramctr_timing *ctrl) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 317 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 318 | /* Save the MRC S3 restore data to cbmem */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 319 | mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl)); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 320 | } |
| 321 | |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 322 | static void reinit_ctrl(ramctr_timing *ctrl, const u32 cpuid) |
Patrick Rudolph | 05d4bf7e | 2017-10-28 16:36:09 +0200 | [diff] [blame] | 323 | { |
| 324 | /* Reset internal state */ |
| 325 | memset(ctrl, 0, sizeof(*ctrl)); |
Patrick Rudolph | 05d4bf7e | 2017-10-28 16:36:09 +0200 | [diff] [blame] | 326 | |
| 327 | /* Get architecture */ |
| 328 | ctrl->cpu = cpuid; |
| 329 | |
| 330 | /* Get ECC support and mode */ |
| 331 | ctrl->ecc_forced = get_host_ecc_forced(); |
| 332 | ctrl->ecc_supported = ctrl->ecc_forced || get_host_ecc_cap(); |
| 333 | printk(BIOS_DEBUG, "ECC supported: %s ECC forced: %s\n", |
| 334 | ctrl->ecc_supported ? "yes" : "no", |
| 335 | ctrl->ecc_forced ? "yes" : "no"); |
| 336 | } |
| 337 | |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 338 | static void init_dram_ddr3(int s3resume, const u32 cpuid) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 339 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 340 | int me_uma_size, cbmem_was_inited, fast_boot, err; |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 341 | ramctr_timing ctrl; |
Elyes Haouas | 78ba7a7 | 2024-05-06 05:11:28 +0200 | [diff] [blame] | 342 | spd_ddr3_raw_data spds[4]; |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 343 | size_t mrc_size; |
Angel Pons | a6a6418 | 2020-03-21 18:06:03 +0100 | [diff] [blame] | 344 | ramctr_timing *ctrl_cached = NULL; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 345 | |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 346 | timestamp_add_now(TS_INITRAM_START); |
Kyösti Mälkki | b33c6fb | 2021-02-17 20:43:04 +0200 | [diff] [blame] | 347 | |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 348 | mchbar_setbits32(SAPMCTL, 1 << 0); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 349 | |
| 350 | /* Wait for ME to be ready */ |
| 351 | intel_early_me_init(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 352 | me_uma_size = intel_early_me_uma_size(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 353 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 354 | printk(BIOS_DEBUG, "Starting native Platform init\n"); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 355 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 356 | wait_txt_clear(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 357 | |
Angel Pons | 5db1b15 | 2020-12-13 16:37:53 +0100 | [diff] [blame] | 358 | wrmsr(0x2e6, (msr_t) { .lo = 0, .hi = 0 }); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 359 | |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 360 | const u32 sskpd = mchbar_read32(SSKPD); // !!! = 0x00000000 |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 361 | if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 && sskpd && !s3resume) { |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 362 | mchbar_write32(SSKPD, 0); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 363 | /* Need reset */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 364 | system_reset(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 365 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 366 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 367 | early_pch_init_native(); |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 368 | early_init_dmi(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 369 | early_thermal_init(); |
| 370 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 371 | /* Try to find timings in MRC cache */ |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 372 | ctrl_cached = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, |
| 373 | MRC_CACHE_VERSION, |
| 374 | &mrc_size); |
| 375 | if (mrc_size < sizeof(ctrl)) |
| 376 | ctrl_cached = NULL; |
Angel Pons | a6a6418 | 2020-03-21 18:06:03 +0100 | [diff] [blame] | 377 | |
| 378 | /* Before reusing training data, assert that the CPU has not been replaced */ |
| 379 | if (ctrl_cached && cpuid != ctrl_cached->cpu) { |
Angel Pons | a6a6418 | 2020-03-21 18:06:03 +0100 | [diff] [blame] | 380 | /* It is not really worrying on a cold boot, but fatal when resuming from S3 */ |
| 381 | printk(s3resume ? BIOS_ALERT : BIOS_NOTICE, |
| 382 | "CPUID %x differs from stored CPUID %x, CPU was replaced!\n", |
| 383 | cpuid, ctrl_cached->cpu); |
| 384 | |
| 385 | /* Invalidate the stored data, it likely does not apply to the current CPU */ |
| 386 | ctrl_cached = NULL; |
| 387 | } |
| 388 | |
| 389 | if (s3resume && !ctrl_cached) { |
| 390 | /* S3 resume is impossible, reset to come up cleanly */ |
| 391 | system_reset(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 392 | } |
| 393 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 394 | /* Verify MRC cache for fast boot */ |
Kyösti Mälkki | 38cb822 | 2016-11-18 19:25:52 +0200 | [diff] [blame] | 395 | if (!s3resume && ctrl_cached) { |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 396 | /* Load SPD unique information data. */ |
| 397 | memset(spds, 0, sizeof(spds)); |
| 398 | mainboard_get_spd(spds, 1); |
| 399 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 400 | /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ |
| 401 | fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached); |
| 402 | if (!fast_boot) |
| 403 | printk(BIOS_DEBUG, "Stored timings CRC16 mismatch.\n"); |
Kyösti Mälkki | 38cb822 | 2016-11-18 19:25:52 +0200 | [diff] [blame] | 404 | } else { |
| 405 | fast_boot = s3resume; |
| 406 | } |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 407 | |
| 408 | if (fast_boot) { |
| 409 | printk(BIOS_DEBUG, "Trying stored timings.\n"); |
| 410 | memcpy(&ctrl, ctrl_cached, sizeof(ctrl)); |
| 411 | |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 412 | err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 413 | if (err) { |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 414 | if (s3resume) { |
| 415 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 416 | system_reset(); |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 417 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 418 | /* No need to erase bad MRC cache here, it gets overwritten on a |
| 419 | successful boot */ |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 420 | printk(BIOS_ERR, "Stored timings are invalid !\n"); |
| 421 | fast_boot = 0; |
| 422 | } |
| 423 | } |
| 424 | if (!fast_boot) { |
Patrick Rudolph | e74ad21 | 2016-11-16 18:06:50 +0100 | [diff] [blame] | 425 | /* Reset internal state */ |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 426 | reinit_ctrl(&ctrl, cpuid); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 427 | |
Patrick Rudolph | 05d4bf7e | 2017-10-28 16:36:09 +0200 | [diff] [blame] | 428 | printk(BIOS_INFO, "ECC RAM %s.\n", ctrl.ecc_forced ? "required" : |
| 429 | ctrl.ecc_supported ? "supported" : "unsupported"); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 430 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 431 | /* Get DDR3 SPD data */ |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 432 | memset(spds, 0, sizeof(spds)); |
| 433 | mainboard_get_spd(spds, 0); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 434 | dram_find_spds_ddr3(spds, &ctrl); |
| 435 | |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 436 | err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 437 | } |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 438 | |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 439 | if (err) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 440 | /* Fallback: disable failing channel */ |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 441 | printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); |
| 442 | printram("Disable failing channel.\n"); |
| 443 | |
Patrick Rudolph | e74ad21 | 2016-11-16 18:06:50 +0100 | [diff] [blame] | 444 | /* Reset internal state */ |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 445 | reinit_ctrl(&ctrl, cpuid); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 446 | |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 447 | /* Reset DDR3 frequency */ |
| 448 | dram_find_spds_ddr3(spds, &ctrl); |
| 449 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 450 | /* Disable failing channel */ |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 451 | disable_channel(&ctrl, GET_ERR_CHANNEL(err)); |
| 452 | |
| 453 | err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); |
| 454 | } |
| 455 | |
Patrick Rudolph | 31d1959 | 2016-03-26 12:22:34 +0100 | [diff] [blame] | 456 | if (err) |
| 457 | die("raminit failed"); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 458 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 459 | /* FIXME: should be hardware revision-dependent. The register only exists on IVB. */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 460 | mchbar_write32(CHANNEL_HASH, 0x00a030ce); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 461 | |
| 462 | set_scrambling_seed(&ctrl); |
| 463 | |
Patrick Rudolph | d058131 | 2020-05-01 18:31:48 +0200 | [diff] [blame] | 464 | if (!s3resume && ctrl.ecc_enabled) |
| 465 | channel_scrub(&ctrl); |
| 466 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 467 | set_normal_operation(&ctrl); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 468 | |
| 469 | final_registers(&ctrl); |
| 470 | |
Patrick Rudolph | d058131 | 2020-05-01 18:31:48 +0200 | [diff] [blame] | 471 | /* can't do this earlier because it needs to be done in normal operation */ |
| 472 | if (CONFIG(DEBUG_RAM_SETUP) && !s3resume && ctrl.ecc_enabled) { |
| 473 | uint32_t i, tseg = pci_read_config32(HOST_BRIDGE, TSEGMB); |
| 474 | |
| 475 | printk(BIOS_INFO, "RAMINIT: ECC scrub test on first channel up to 0x%x\n", |
| 476 | tseg); |
| 477 | |
| 478 | /* |
| 479 | * This test helps to debug the ECC scrubbing. |
| 480 | * It likely tests every channel/rank, as rank interleave and enhanced |
| 481 | * interleave are enabled, but there's no guarantee for it. |
| 482 | */ |
| 483 | |
| 484 | /* Skip first MB to avoid special case for A-seg and test up to TSEG */ |
| 485 | for (i = 1; i < tseg >> 20; i++) { |
| 486 | for (int j = 0; j < 1 * MiB; j += 4096) { |
| 487 | uintptr_t addr = i * MiB + j; |
| 488 | if (read32((u32 *)addr) == 0) |
| 489 | continue; |
| 490 | |
| 491 | printk(BIOS_ERR, "RAMINIT: ECC scrub: DRAM not cleared at" |
| 492 | " addr 0x%lx\n", addr); |
| 493 | break; |
| 494 | } |
| 495 | } |
| 496 | printk(BIOS_INFO, "RAMINIT: ECC scrub test done.\n"); |
| 497 | } |
| 498 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 499 | /* Zone config */ |
| 500 | dram_zones(&ctrl, 0); |
| 501 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 502 | intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); |
| 503 | intel_early_me_status(); |
| 504 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 505 | report_memory_config(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 506 | |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 507 | timestamp_add_now(TS_INITRAM_END); |
Kyösti Mälkki | b33c6fb | 2021-02-17 20:43:04 +0200 | [diff] [blame] | 508 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 509 | cbmem_was_inited = !cbmem_recovery(s3resume); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 510 | if (!fast_boot) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 511 | save_timings(&ctrl); |
| 512 | if (s3resume && !cbmem_was_inited) { |
| 513 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 514 | system_reset(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 515 | } |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 516 | |
Nico Huber | 9ce5974 | 2018-09-13 10:52:44 +0200 | [diff] [blame] | 517 | if (!s3resume) |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 518 | setup_sdram_meminfo(&ctrl); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 519 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 520 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 521 | void perform_raminit(int s3resume) |
| 522 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 523 | post_code(0x3a); |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 524 | init_dram_ddr3(s3resume, cpu_get_cpuid()); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 525 | } |