Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Elyes HAOUAS | 3081855 | 2019-06-23 07:03:59 +0200 | [diff] [blame] | 2 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 3 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 4 | #include <device/mmio.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 5 | #include <stdint.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 6 | #include <device/device.h> |
| 7 | #include <soc/nvidia/tegra/dc.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 8 | #include <soc/display.h> |
Patrick Rudolph | 8b56c8c | 2020-02-19 12:57:00 +0100 | [diff] [blame^] | 9 | #include <framebuffer_info.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 10 | |
Elyes HAOUAS | 3081855 | 2019-06-23 07:03:59 +0200 | [diff] [blame] | 11 | #include "chip.h" |
| 12 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 13 | int dump = 0; |
Elyes HAOUAS | 39303d5 | 2018-07-08 12:40:45 +0200 | [diff] [blame] | 14 | unsigned long READL(void *p) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 15 | { |
Elyes HAOUAS | 88607a4 | 2018-10-05 10:36:45 +0200 | [diff] [blame] | 16 | unsigned long value; |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 17 | |
| 18 | /* |
| 19 | * In case of hard hung on readl(p), we can set dump > 1 to print out |
| 20 | * the address accessed. |
| 21 | */ |
Elyes HAOUAS | 88607a4 | 2018-10-05 10:36:45 +0200 | [diff] [blame] | 22 | if (dump > 1) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 23 | printk(BIOS_SPEW, "readl %p\n", p); |
| 24 | |
Elyes HAOUAS | 88607a4 | 2018-10-05 10:36:45 +0200 | [diff] [blame] | 25 | value = read32(p); |
| 26 | if (dump) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 27 | printk(BIOS_SPEW, "readl %p %08lx\n", p, value); |
Elyes HAOUAS | 88607a4 | 2018-10-05 10:36:45 +0200 | [diff] [blame] | 28 | return value; |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 29 | } |
| 30 | |
Elyes HAOUAS | 39303d5 | 2018-07-08 12:40:45 +0200 | [diff] [blame] | 31 | void WRITEL(unsigned long value, void *p) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 32 | { |
Elyes HAOUAS | 88607a4 | 2018-10-05 10:36:45 +0200 | [diff] [blame] | 33 | if (dump) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 34 | printk(BIOS_SPEW, "writel %p %08lx\n", p, value); |
Elyes HAOUAS | 88607a4 | 2018-10-05 10:36:45 +0200 | [diff] [blame] | 35 | write32(p, value); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 36 | } |
| 37 | |
| 38 | /* return in 1000ths of a Hertz */ |
| 39 | static int tegra_calc_refresh(const struct soc_nvidia_tegra210_config *config) |
| 40 | { |
| 41 | int refresh; |
| 42 | int h_total = htotal(config); |
| 43 | int v_total = vtotal(config); |
| 44 | int pclk = config->pixel_clock; |
| 45 | |
| 46 | if (!pclk || !h_total || !v_total) |
| 47 | return 0; |
| 48 | refresh = pclk / h_total; |
| 49 | refresh *= 1000; |
| 50 | refresh /= v_total; |
| 51 | return refresh; |
| 52 | } |
| 53 | |
| 54 | static void print_mode(const struct soc_nvidia_tegra210_config *config) |
| 55 | { |
| 56 | if (config) { |
| 57 | int refresh = tegra_calc_refresh(config); |
| 58 | printk(BIOS_ERR, |
| 59 | "Panel Mode: %dx%d@%d.%03uHz pclk=%d\n", |
| 60 | config->xres, config->yres, |
| 61 | refresh / 1000, refresh % 1000, |
| 62 | config->pixel_clock); |
| 63 | } |
| 64 | } |
| 65 | |
| 66 | int update_display_mode(struct display_controller *disp_ctrl, |
Elyes HAOUAS | 88607a4 | 2018-10-05 10:36:45 +0200 | [diff] [blame] | 67 | struct soc_nvidia_tegra210_config *config) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 68 | { |
| 69 | print_mode(config); |
| 70 | |
| 71 | printk(BIOS_ERR, "config: xres:yres: %d x %d\n ", |
| 72 | config->xres, config->yres); |
| 73 | printk(BIOS_ERR, " href_sync:vref_sync: %d x %d\n ", |
| 74 | config->href_to_sync, config->vref_to_sync); |
| 75 | printk(BIOS_ERR, " hsyn_width:vsyn_width: %d x %d\n ", |
| 76 | config->hsync_width, config->vsync_width); |
| 77 | printk(BIOS_ERR, " hfnt_porch:vfnt_porch: %d x %d\n ", |
| 78 | config->hfront_porch, config->vfront_porch); |
| 79 | printk(BIOS_ERR, " hbk_porch:vbk_porch: %d x %d\n ", |
| 80 | config->hback_porch, config->vback_porch); |
| 81 | |
| 82 | WRITEL(0x0, &disp_ctrl->disp.disp_timing_opt); |
| 83 | WRITEL(0x0, &disp_ctrl->disp.disp_color_ctrl); |
| 84 | |
| 85 | /* select win opt */ |
| 86 | WRITEL(config->win_opt, &disp_ctrl->disp.disp_win_opt); |
| 87 | |
| 88 | WRITEL(config->vref_to_sync << 16 | config->href_to_sync, |
| 89 | &disp_ctrl->disp.ref_to_sync); |
| 90 | |
| 91 | WRITEL(config->vsync_width << 16 | config->hsync_width, |
| 92 | &disp_ctrl->disp.sync_width); |
| 93 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 94 | WRITEL((config->vback_porch << 16) | config->hback_porch, |
| 95 | &disp_ctrl->disp.back_porch); |
| 96 | |
| 97 | WRITEL((config->vfront_porch << 16) | config->hfront_porch, |
| 98 | &disp_ctrl->disp.front_porch); |
| 99 | |
| 100 | WRITEL(config->xres | (config->yres << 16), |
| 101 | &disp_ctrl->disp.disp_active); |
| 102 | |
| 103 | /* |
| 104 | * PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv. |
| 105 | * |
| 106 | * default: Set both shift_clk_div and pixel_clock_div to 1 |
| 107 | */ |
| 108 | update_display_shift_clock_divider(disp_ctrl, SHIFT_CLK_DIVIDER(1)); |
| 109 | |
| 110 | return 0; |
| 111 | } |
| 112 | |
| 113 | void update_display_shift_clock_divider(struct display_controller *disp_ctrl, |
Elyes HAOUAS | 88607a4 | 2018-10-05 10:36:45 +0200 | [diff] [blame] | 114 | u32 shift_clock_div) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 115 | { |
| 116 | WRITEL((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) | |
| 117 | (shift_clock_div & 0xff) << SHIFT_CLK_DIVIDER_SHIFT, |
| 118 | &disp_ctrl->disp.disp_clk_ctrl); |
| 119 | printk(BIOS_DEBUG, "%s: ShiftClockDiv=%u\n", |
| 120 | __func__, shift_clock_div); |
| 121 | } |
| 122 | |
| 123 | /* |
| 124 | * update_window: |
| 125 | * set up window registers and activate window except two: |
| 126 | * frame buffer base address register (WINBUF_START_ADDR) and |
| 127 | * display enable register (_DISP_DISP_WIN_OPTIONS). This is |
Paul Kocialkowski | 536f5a7 | 2016-05-07 14:31:35 +0200 | [diff] [blame] | 128 | * because framebuffer is not available until payload stage. |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 129 | */ |
| 130 | void update_window(const struct soc_nvidia_tegra210_config *config) |
| 131 | { |
| 132 | struct display_controller *disp_ctrl = |
| 133 | (void *)config->display_controller; |
| 134 | u32 val; |
| 135 | |
| 136 | WRITEL(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header); |
| 137 | |
| 138 | WRITEL(((config->yres << 16) | config->xres), &disp_ctrl->win.size); |
| 139 | |
| 140 | WRITEL(((config->display_yres << 16) | |
| 141 | (config->display_xres * |
| 142 | config->framebuffer_bits_per_pixel / 8)), |
| 143 | &disp_ctrl->win.prescaled_size); |
| 144 | |
| 145 | val = ALIGN_UP((config->display_xres * |
| 146 | config->framebuffer_bits_per_pixel / 8), 64); |
| 147 | WRITEL(val, &disp_ctrl->win.line_stride); |
| 148 | |
| 149 | WRITEL(config->color_depth, &disp_ctrl->win.color_depth); |
| 150 | WRITEL(COLOR_BLACK, &disp_ctrl->disp.blend_background_color); |
| 151 | |
| 152 | WRITEL(((DDA_INC(config->display_yres, config->yres) << 16) | |
| 153 | DDA_INC(config->display_xres, config->xres)), |
| 154 | &disp_ctrl->win.dda_increment); |
| 155 | |
| 156 | WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd); |
| 157 | |
| 158 | WRITEL(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); |
| 159 | |
| 160 | WRITEL(0, &disp_ctrl->win.buffer_addr_mode); |
| 161 | |
| 162 | val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | |
| 163 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; |
| 164 | WRITEL(val, &disp_ctrl->cmd.disp_pow_ctrl); |
| 165 | |
| 166 | val = GENERAL_UPDATE | WIN_A_UPDATE; |
| 167 | WRITEL(val, &disp_ctrl->cmd.state_ctrl); |
| 168 | |
| 169 | val = GENERAL_ACT_REQ | WIN_A_ACT_REQ; |
| 170 | WRITEL(val, &disp_ctrl->cmd.state_ctrl); |
| 171 | } |
| 172 | |
| 173 | int tegra_dc_init(struct display_controller *disp_ctrl) |
| 174 | { |
| 175 | /* do not accept interrupts during initialization */ |
| 176 | WRITEL(0x00000000, &disp_ctrl->cmd.int_mask); |
| 177 | WRITEL(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, |
| 178 | &disp_ctrl->cmd.state_access); |
| 179 | WRITEL(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header); |
| 180 | WRITEL(0x00000000, &disp_ctrl->win.win_opt); |
| 181 | WRITEL(0x00000000, &disp_ctrl->win.byte_swap); |
| 182 | WRITEL(0x00000000, &disp_ctrl->win.buffer_ctrl); |
| 183 | |
| 184 | WRITEL(0x00000000, &disp_ctrl->win.pos); |
| 185 | WRITEL(0x00000000, &disp_ctrl->win.h_initial_dda); |
| 186 | WRITEL(0x00000000, &disp_ctrl->win.v_initial_dda); |
| 187 | WRITEL(0x00000000, &disp_ctrl->win.dda_increment); |
| 188 | WRITEL(0x00000000, &disp_ctrl->win.dv_ctrl); |
| 189 | |
| 190 | WRITEL(0x01000000, &disp_ctrl->win.blend_layer_ctrl); |
| 191 | WRITEL(0x00000000, &disp_ctrl->win.blend_match_select); |
| 192 | WRITEL(0x00000000, &disp_ctrl->win.blend_nomatch_select); |
| 193 | WRITEL(0x00000000, &disp_ctrl->win.blend_alpha_1bit); |
| 194 | |
| 195 | WRITEL(0x00000000, &disp_ctrl->winbuf.start_addr_hi); |
| 196 | WRITEL(0x00000000, &disp_ctrl->winbuf.addr_h_offset); |
| 197 | WRITEL(0x00000000, &disp_ctrl->winbuf.addr_v_offset); |
| 198 | |
| 199 | WRITEL(0x00000000, &disp_ctrl->com.crc_checksum); |
| 200 | WRITEL(0x00000000, &disp_ctrl->com.pin_output_enb[0]); |
| 201 | WRITEL(0x00000000, &disp_ctrl->com.pin_output_enb[1]); |
| 202 | WRITEL(0x00000000, &disp_ctrl->com.pin_output_enb[2]); |
| 203 | WRITEL(0x00000000, &disp_ctrl->com.pin_output_enb[3]); |
| 204 | WRITEL(0x00000000, &disp_ctrl->disp.disp_signal_opt0); |
| 205 | |
| 206 | return 0; |
| 207 | } |
| 208 | |
| 209 | /* |
| 210 | * Save mode to cb tables |
| 211 | */ |
| 212 | void pass_mode_info_to_payload( |
| 213 | struct soc_nvidia_tegra210_config *config) |
| 214 | { |
Patrick Rudolph | 8b56c8c | 2020-02-19 12:57:00 +0100 | [diff] [blame^] | 215 | const uint32_t bytes_per_line = ALIGN_UP(config->display_xres * |
| 216 | DIV_ROUND_UP(config->framebuffer_bits_per_pixel, 8), 64); |
| 217 | /* The framebuffer address is zero to let the payload allocate it */ |
| 218 | fb_add_framebuffer_info(0, config->display_xres, config->display_yres, |
| 219 | bytes_per_line, config->framebuffer_bits_per_pixel); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 220 | } |