blob: 46443cfe72e4c4a301b675d418f1bf89ab1d5f80 [file] [log] [blame]
Patrick Georgi40a3e322015-06-22 19:41:29 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2014 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Patrick Georgi40a3e322015-06-22 19:41:29 +020014 */
Elyes HAOUAS30818552019-06-23 07:03:59 +020015
Patrick Georgi40a3e322015-06-22 19:41:29 +020016#include <console/console.h>
Kyösti Mälkki13f66502019-03-03 08:01:05 +020017#include <device/mmio.h>
Patrick Georgi40a3e322015-06-22 19:41:29 +020018#include <stdint.h>
Patrick Georgi40a3e322015-06-22 19:41:29 +020019#include <edid.h>
20#include <device/device.h>
21#include <soc/nvidia/tegra/dc.h>
Patrick Georgi40a3e322015-06-22 19:41:29 +020022#include <soc/display.h>
23
Elyes HAOUAS30818552019-06-23 07:03:59 +020024#include "chip.h"
25
Patrick Georgi40a3e322015-06-22 19:41:29 +020026int dump = 0;
Elyes HAOUAS39303d52018-07-08 12:40:45 +020027unsigned long READL(void *p)
Patrick Georgi40a3e322015-06-22 19:41:29 +020028{
Elyes HAOUAS88607a42018-10-05 10:36:45 +020029 unsigned long value;
Patrick Georgi40a3e322015-06-22 19:41:29 +020030
31 /*
32 * In case of hard hung on readl(p), we can set dump > 1 to print out
33 * the address accessed.
34 */
Elyes HAOUAS88607a42018-10-05 10:36:45 +020035 if (dump > 1)
Patrick Georgi40a3e322015-06-22 19:41:29 +020036 printk(BIOS_SPEW, "readl %p\n", p);
37
Elyes HAOUAS88607a42018-10-05 10:36:45 +020038 value = read32(p);
39 if (dump)
Patrick Georgi40a3e322015-06-22 19:41:29 +020040 printk(BIOS_SPEW, "readl %p %08lx\n", p, value);
Elyes HAOUAS88607a42018-10-05 10:36:45 +020041 return value;
Patrick Georgi40a3e322015-06-22 19:41:29 +020042}
43
Elyes HAOUAS39303d52018-07-08 12:40:45 +020044void WRITEL(unsigned long value, void *p)
Patrick Georgi40a3e322015-06-22 19:41:29 +020045{
Elyes HAOUAS88607a42018-10-05 10:36:45 +020046 if (dump)
Patrick Georgi40a3e322015-06-22 19:41:29 +020047 printk(BIOS_SPEW, "writel %p %08lx\n", p, value);
Elyes HAOUAS88607a42018-10-05 10:36:45 +020048 write32(p, value);
Patrick Georgi40a3e322015-06-22 19:41:29 +020049}
50
51/* return in 1000ths of a Hertz */
52static int tegra_calc_refresh(const struct soc_nvidia_tegra210_config *config)
53{
54 int refresh;
55 int h_total = htotal(config);
56 int v_total = vtotal(config);
57 int pclk = config->pixel_clock;
58
59 if (!pclk || !h_total || !v_total)
60 return 0;
61 refresh = pclk / h_total;
62 refresh *= 1000;
63 refresh /= v_total;
64 return refresh;
65}
66
67static void print_mode(const struct soc_nvidia_tegra210_config *config)
68{
69 if (config) {
70 int refresh = tegra_calc_refresh(config);
71 printk(BIOS_ERR,
72 "Panel Mode: %dx%d@%d.%03uHz pclk=%d\n",
73 config->xres, config->yres,
74 refresh / 1000, refresh % 1000,
75 config->pixel_clock);
76 }
77}
78
79int update_display_mode(struct display_controller *disp_ctrl,
Elyes HAOUAS88607a42018-10-05 10:36:45 +020080 struct soc_nvidia_tegra210_config *config)
Patrick Georgi40a3e322015-06-22 19:41:29 +020081{
82 print_mode(config);
83
84 printk(BIOS_ERR, "config: xres:yres: %d x %d\n ",
85 config->xres, config->yres);
86 printk(BIOS_ERR, " href_sync:vref_sync: %d x %d\n ",
87 config->href_to_sync, config->vref_to_sync);
88 printk(BIOS_ERR, " hsyn_width:vsyn_width: %d x %d\n ",
89 config->hsync_width, config->vsync_width);
90 printk(BIOS_ERR, " hfnt_porch:vfnt_porch: %d x %d\n ",
91 config->hfront_porch, config->vfront_porch);
92 printk(BIOS_ERR, " hbk_porch:vbk_porch: %d x %d\n ",
93 config->hback_porch, config->vback_porch);
94
95 WRITEL(0x0, &disp_ctrl->disp.disp_timing_opt);
96 WRITEL(0x0, &disp_ctrl->disp.disp_color_ctrl);
97
98 /* select win opt */
99 WRITEL(config->win_opt, &disp_ctrl->disp.disp_win_opt);
100
101 WRITEL(config->vref_to_sync << 16 | config->href_to_sync,
102 &disp_ctrl->disp.ref_to_sync);
103
104 WRITEL(config->vsync_width << 16 | config->hsync_width,
105 &disp_ctrl->disp.sync_width);
106
107
108 WRITEL((config->vback_porch << 16) | config->hback_porch,
109 &disp_ctrl->disp.back_porch);
110
111 WRITEL((config->vfront_porch << 16) | config->hfront_porch,
112 &disp_ctrl->disp.front_porch);
113
114 WRITEL(config->xres | (config->yres << 16),
115 &disp_ctrl->disp.disp_active);
116
117 /*
118 * PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv.
119 *
120 * default: Set both shift_clk_div and pixel_clock_div to 1
121 */
122 update_display_shift_clock_divider(disp_ctrl, SHIFT_CLK_DIVIDER(1));
123
124 return 0;
125}
126
127void update_display_shift_clock_divider(struct display_controller *disp_ctrl,
Elyes HAOUAS88607a42018-10-05 10:36:45 +0200128 u32 shift_clock_div)
Patrick Georgi40a3e322015-06-22 19:41:29 +0200129{
130 WRITEL((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) |
131 (shift_clock_div & 0xff) << SHIFT_CLK_DIVIDER_SHIFT,
132 &disp_ctrl->disp.disp_clk_ctrl);
133 printk(BIOS_DEBUG, "%s: ShiftClockDiv=%u\n",
134 __func__, shift_clock_div);
135}
136
137/*
138 * update_window:
139 * set up window registers and activate window except two:
140 * frame buffer base address register (WINBUF_START_ADDR) and
141 * display enable register (_DISP_DISP_WIN_OPTIONS). This is
Paul Kocialkowski536f5a72016-05-07 14:31:35 +0200142 * because framebuffer is not available until payload stage.
Patrick Georgi40a3e322015-06-22 19:41:29 +0200143 */
144void update_window(const struct soc_nvidia_tegra210_config *config)
145{
146 struct display_controller *disp_ctrl =
147 (void *)config->display_controller;
148 u32 val;
149
150 WRITEL(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
151
152 WRITEL(((config->yres << 16) | config->xres), &disp_ctrl->win.size);
153
154 WRITEL(((config->display_yres << 16) |
155 (config->display_xres *
156 config->framebuffer_bits_per_pixel / 8)),
157 &disp_ctrl->win.prescaled_size);
158
159 val = ALIGN_UP((config->display_xres *
160 config->framebuffer_bits_per_pixel / 8), 64);
161 WRITEL(val, &disp_ctrl->win.line_stride);
162
163 WRITEL(config->color_depth, &disp_ctrl->win.color_depth);
164 WRITEL(COLOR_BLACK, &disp_ctrl->disp.blend_background_color);
165
166 WRITEL(((DDA_INC(config->display_yres, config->yres) << 16) |
167 DDA_INC(config->display_xres, config->xres)),
168 &disp_ctrl->win.dda_increment);
169
170 WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd);
171
172 WRITEL(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
173
174 WRITEL(0, &disp_ctrl->win.buffer_addr_mode);
175
176 val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
177 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
178 WRITEL(val, &disp_ctrl->cmd.disp_pow_ctrl);
179
180 val = GENERAL_UPDATE | WIN_A_UPDATE;
181 WRITEL(val, &disp_ctrl->cmd.state_ctrl);
182
183 val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
184 WRITEL(val, &disp_ctrl->cmd.state_ctrl);
185}
186
187int tegra_dc_init(struct display_controller *disp_ctrl)
188{
189 /* do not accept interrupts during initialization */
190 WRITEL(0x00000000, &disp_ctrl->cmd.int_mask);
191 WRITEL(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
192 &disp_ctrl->cmd.state_access);
193 WRITEL(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
194 WRITEL(0x00000000, &disp_ctrl->win.win_opt);
195 WRITEL(0x00000000, &disp_ctrl->win.byte_swap);
196 WRITEL(0x00000000, &disp_ctrl->win.buffer_ctrl);
197
198 WRITEL(0x00000000, &disp_ctrl->win.pos);
199 WRITEL(0x00000000, &disp_ctrl->win.h_initial_dda);
200 WRITEL(0x00000000, &disp_ctrl->win.v_initial_dda);
201 WRITEL(0x00000000, &disp_ctrl->win.dda_increment);
202 WRITEL(0x00000000, &disp_ctrl->win.dv_ctrl);
203
204 WRITEL(0x01000000, &disp_ctrl->win.blend_layer_ctrl);
205 WRITEL(0x00000000, &disp_ctrl->win.blend_match_select);
206 WRITEL(0x00000000, &disp_ctrl->win.blend_nomatch_select);
207 WRITEL(0x00000000, &disp_ctrl->win.blend_alpha_1bit);
208
209 WRITEL(0x00000000, &disp_ctrl->winbuf.start_addr_hi);
210 WRITEL(0x00000000, &disp_ctrl->winbuf.addr_h_offset);
211 WRITEL(0x00000000, &disp_ctrl->winbuf.addr_v_offset);
212
213 WRITEL(0x00000000, &disp_ctrl->com.crc_checksum);
214 WRITEL(0x00000000, &disp_ctrl->com.pin_output_enb[0]);
215 WRITEL(0x00000000, &disp_ctrl->com.pin_output_enb[1]);
216 WRITEL(0x00000000, &disp_ctrl->com.pin_output_enb[2]);
217 WRITEL(0x00000000, &disp_ctrl->com.pin_output_enb[3]);
218 WRITEL(0x00000000, &disp_ctrl->disp.disp_signal_opt0);
219
220 return 0;
221}
222
223/*
224 * Save mode to cb tables
225 */
226void pass_mode_info_to_payload(
227 struct soc_nvidia_tegra210_config *config)
228{
229 struct edid edid;
Julius Werner69112192016-03-14 17:29:55 -0700230
231 edid.mode.va = config->display_yres;
232 edid.mode.ha = config->display_xres;
233 edid_set_framebuffer_bits_per_pixel(&edid,
Paul Kocialkowski0dcd4172016-05-07 14:30:24 +0200234 config->framebuffer_bits_per_pixel, 64);
Patrick Georgi40a3e322015-06-22 19:41:29 +0200235
236 printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n "
237 " x_res x y_res: %d x %d, size: %d\n",
238 __func__, edid.bytes_per_line,
239 edid.framebuffer_bits_per_pixel,
240 edid.x_resolution, edid.y_resolution,
241 (edid.bytes_per_line * edid.y_resolution));
242
243 set_vbe_mode_info_valid(&edid, 0);
244}