Hannah Williams | 5e83e8b | 2018-02-09 18:35:17 -0800 | [diff] [blame] | 1 | chip soc/intel/apollolake |
| 2 | device cpu_cluster 0 on |
| 3 | device lapic 0 on end |
| 4 | end |
Shamile Khan | c5f354b | 2018-02-22 13:45:39 -0800 | [diff] [blame] | 5 | |
Furquan Shaikh | ade3bc5 | 2018-03-28 11:53:37 -0700 | [diff] [blame] | 6 | register "pcie_rp_clkreq_pin[2]" = "3" # wifi/bt |
Shamile Khan | 25c1781 | 2018-03-19 17:03:48 -0700 | [diff] [blame] | 7 | # Disable unused clkreq of PCIe root ports |
Furquan Shaikh | ade3bc5 | 2018-03-28 11:53:37 -0700 | [diff] [blame] | 8 | register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" |
Shamile Khan | 25c1781 | 2018-03-19 17:03:48 -0700 | [diff] [blame] | 9 | register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" |
Shamile Khan | 25c1781 | 2018-03-19 17:03:48 -0700 | [diff] [blame] | 10 | register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" |
| 11 | register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" |
| 12 | register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" |
| 13 | |
| 14 | # Set de-emphasis to disabled for PCIE WiFI (Thunderpeak) |
| 15 | # as it is required for detection |
Furquan Shaikh | ade3bc5 | 2018-03-28 11:53:37 -0700 | [diff] [blame] | 16 | register "pcie_rp_deemphasis_enable[2]" = "0" |
Shamile Khan | 25c1781 | 2018-03-19 17:03:48 -0700 | [diff] [blame] | 17 | # Set de-emphasis to default (enabled) for remaining ports |
Furquan Shaikh | ade3bc5 | 2018-03-28 11:53:37 -0700 | [diff] [blame] | 18 | register "pcie_rp_deemphasis_enable[0]" = "1" |
Shamile Khan | 25c1781 | 2018-03-19 17:03:48 -0700 | [diff] [blame] | 19 | register "pcie_rp_deemphasis_enable[1]" = "1" |
Shamile Khan | 25c1781 | 2018-03-19 17:03:48 -0700 | [diff] [blame] | 20 | register "pcie_rp_deemphasis_enable[3]" = "1" |
| 21 | register "pcie_rp_deemphasis_enable[4]" = "1" |
| 22 | register "pcie_rp_deemphasis_enable[5]" = "1" |
| 23 | |
Justin TerAvest | 3cb00ef | 2018-03-16 12:50:13 -0600 | [diff] [blame] | 24 | # GPIO for PERST_0 (WLAN_PE_RST) |
| 25 | register "prt0_gpio" = "GPIO_164" |
| 26 | |
Shamile Khan | c5f354b | 2018-02-22 13:45:39 -0800 | [diff] [blame] | 27 | # GPE configuration |
| 28 | # Note that GPE events called out in ASL code rely on this |
| 29 | # route, i.e., if this route changes then the affected GPE |
| 30 | # offset bits also need to be changed. This sets the PMC register |
| 31 | # GPE_CFG fields. |
Furquan Shaikh | 1313244 | 2018-06-07 15:27:14 -0700 | [diff] [blame] | 32 | # DW1 is used by: |
| 33 | # - GPIO_63 - H1_PCH_INT_ODL |
| 34 | # DW2 is used by: |
| 35 | # - GPIO_141 - EC_PCH_WAKE_ODL |
| 36 | # - GPIO_142 - TRACKPAD_INT2_1V8_ODL |
| 37 | # - GPIO_144 - PEN_EJECT_ODL |
| 38 | # DW3 is used by: |
| 39 | # - GPIO_117 - LTE_WAKE_ODL |
| 40 | # - GPIO_119 - WLAN_PCIE_WAKE_ODL |
| 41 | register "gpe0_dw1" = "PMC_GPE_NW_63_32" |
Shamile Khan | c5f354b | 2018-02-22 13:45:39 -0800 | [diff] [blame] | 42 | register "gpe0_dw2" = "PMC_GPE_N_95_64" |
Furquan Shaikh | 1313244 | 2018-06-07 15:27:14 -0700 | [diff] [blame] | 43 | register "gpe0_dw3" = "PMC_GPE_N_63_32" |
Shamile Khan | c5f354b | 2018-02-22 13:45:39 -0800 | [diff] [blame] | 44 | |
Sumeet Pawnikar | f5fd9a3 | 2018-08-03 12:17:34 +0530 | [diff] [blame] | 45 | # PL1 override 10000 mW: Due to error in the energy calculation for |
Sumeet Pawnikar | 65d2d21 | 2018-03-23 23:30:43 +0530 | [diff] [blame] | 46 | # current VR solution. Experiments show that SoC TDP max (6W) can |
Sumeet Pawnikar | f5fd9a3 | 2018-08-03 12:17:34 +0530 | [diff] [blame] | 47 | # be reached when RAPL PL1 is set to 10W. |
| 48 | register "tdp_pl1_override_mw" = "10000" |
Sumeet Pawnikar | 65d2d21 | 2018-03-23 23:30:43 +0530 | [diff] [blame] | 49 | # Set RAPL PL2 to 15W. |
| 50 | register "tdp_pl2_override_mw" = "15000" |
| 51 | |
Shamile Khan | c5f354b | 2018-02-22 13:45:39 -0800 | [diff] [blame] | 52 | # Minimum SLP S3 assertion width 28ms. |
| 53 | register "slp_s3_assertion_width_usecs" = "28000" |
| 54 | |
| 55 | # Enable lpss s0ix |
| 56 | register "lpss_s0ix_enable" = "1" |
| 57 | |
Sumeet Pawnikar | 7efdacd | 2018-03-23 22:47:45 +0530 | [diff] [blame] | 58 | # Enable DPTF |
| 59 | register "dptf_enable" = "1" |
| 60 | |
Shamile Khan | cb9f55e | 2018-03-12 16:54:53 -0700 | [diff] [blame] | 61 | # Enable Audio Clock and Power gating |
| 62 | register "hdaudio_clk_gate_enable" = "1" |
| 63 | register "hdaudio_pwr_gate_enable" = "1" |
| 64 | register "hdaudio_bios_config_lockdown" = "1" |
| 65 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 66 | # Intel Common SoC Config |
| 67 | #+-------------------+---------------------------+ |
| 68 | #| Field | Value | |
| 69 | #+-------------------+---------------------------+ |
| 70 | #| GSPI0 | cr50 TPM. Early init is | |
| 71 | #| | required to set up a BAR | |
| 72 | #| | for TPM communication | |
| 73 | #| | before memory is up | |
| 74 | #| I2C0 | Digitizer | |
| 75 | #| I2C5 | Audio | |
| 76 | #| I2C6 | Trackpad | |
| 77 | #| I2C7 | Touchscreen | |
| 78 | #+-------------------+---------------------------+ |
| 79 | register "common_soc_config" = "{ |
| 80 | .gspi[0] = { |
| 81 | .speed_mhz = 1, |
| 82 | .early_init = 1, |
| 83 | }, |
| 84 | .i2c[0] = { |
| 85 | .speed = I2C_SPEED_FAST, |
| 86 | .rise_time_ns = 152, |
| 87 | .fall_time_ns = 30, |
| 88 | }, |
| 89 | .i2c[5] = { |
| 90 | .speed = I2C_SPEED_FAST, |
| 91 | .rise_time_ns = 104, |
| 92 | .fall_time_ns = 52, |
| 93 | }, |
| 94 | .i2c[6] = { |
| 95 | .speed = I2C_SPEED_FAST, |
| 96 | .rise_time_ns = 114, |
| 97 | .fall_time_ns = 164, |
| 98 | .data_hold_time_ns = 350, |
| 99 | }, |
| 100 | .i2c[7] = { |
| 101 | .speed = I2C_SPEED_FAST, |
| 102 | .rise_time_ns = 76, |
| 103 | .fall_time_ns = 164, |
| 104 | }, |
Ravi Sarawadi | c293496 | 2018-02-27 13:57:01 -0800 | [diff] [blame] | 105 | }" |
| 106 | |
Shaunak Saha | ea5c0a1 | 2018-03-21 08:34:17 -0700 | [diff] [blame] | 107 | register "pnp_settings" = "PNP_PERF_POWER" |
| 108 | |
Shamile Khan | c5f354b | 2018-02-22 13:45:39 -0800 | [diff] [blame] | 109 | device domain 0 on |
| 110 | device pci 00.0 on end # - Host Bridge |
| 111 | device pci 00.1 on end # - DPTF |
Shaunak Saha | 55fe082 | 2018-04-23 16:25:44 -0700 | [diff] [blame] | 112 | device pci 00.2 off end # - NPK |
Shamile Khan | c5f354b | 2018-02-22 13:45:39 -0800 | [diff] [blame] | 113 | device pci 02.0 on end # - Gen |
| 114 | device pci 03.0 on end # - Iunit |
Furquan Shaikh | c3cbbe6 | 2018-08-08 18:44:54 -0700 | [diff] [blame] | 115 | chip drivers/intel/wifi |
| 116 | register "wake" = "GPE0A_CNVI_PME_STS" |
| 117 | device pci 0c.0 on end # - CNVi |
| 118 | end |
Shamile Khan | c5f354b | 2018-02-22 13:45:39 -0800 | [diff] [blame] | 119 | device pci 0d.0 on end # - P2SB |
| 120 | device pci 0d.1 on end # - PMC |
| 121 | device pci 0d.2 on end # - Fast SPI |
| 122 | device pci 0d.3 on end # - Shared SRAM |
Shamile Khan | cb9f55e | 2018-03-12 16:54:53 -0700 | [diff] [blame] | 123 | device pci 0e.0 on |
| 124 | chip drivers/generic/max98357a |
| 125 | register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)" |
| 126 | register "sdmode_delay" = "5" |
| 127 | device generic 0 on end |
| 128 | end |
| 129 | end # - Audio |
Shamile Khan | c5f354b | 2018-02-22 13:45:39 -0800 | [diff] [blame] | 130 | device pci 0f.0 on end # - Heci1 |
| 131 | device pci 0f.1 on end # - Heci2 |
| 132 | device pci 0f.2 on end # - Heci3 |
| 133 | device pci 11.0 off end # - ISH |
| 134 | device pci 12.0 off end # - SATA |
Furquan Shaikh | ade3bc5 | 2018-03-28 11:53:37 -0700 | [diff] [blame] | 135 | device pci 13.0 on |
| 136 | chip drivers/intel/wifi |
Furquan Shaikh | 1313244 | 2018-06-07 15:27:14 -0700 | [diff] [blame] | 137 | register "wake" = "GPE0_DW3_11" |
Furquan Shaikh | ade3bc5 | 2018-03-28 11:53:37 -0700 | [diff] [blame] | 138 | device pci 00.0 on end |
| 139 | end |
| 140 | end # - PCIe-A 0 Onboard M2 Slot(Wifi) |
Shamile Khan | c5f354b | 2018-02-22 13:45:39 -0800 | [diff] [blame] | 141 | device pci 13.1 off end # - PCIe-A 1 |
| 142 | device pci 13.2 off end # - PCIe-A 2 |
| 143 | device pci 13.3 off end # - PCIe-A 3 |
| 144 | device pci 14.0 off end # - PCIe-B 0 |
| 145 | device pci 14.1 off end # - PCIe-B 1 |
Karthikeyan Ramasubramanian | cd69259 | 2019-01-28 16:01:13 -0700 | [diff] [blame] | 146 | device pci 15.0 on |
| 147 | chip drivers/usb/acpi |
| 148 | register "desc" = ""Root Hub"" |
| 149 | register "type" = "UPC_TYPE_HUB" |
| 150 | device usb 0.0 on |
| 151 | chip drivers/usb/acpi |
| 152 | register "desc" = ""Bluetooth"" |
| 153 | register "type" = "UPC_TYPE_INTERNAL" |
| 154 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)" |
| 155 | device usb 2.2 on end |
| 156 | end |
Karthikeyan Ramasubramanian | 8a64b6f | 2019-01-31 11:26:50 -0700 | [diff] [blame^] | 157 | chip drivers/usb/acpi |
| 158 | register "desc" = ""Bluetooth"" |
| 159 | register "type" = "UPC_TYPE_INTERNAL" |
| 160 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)" |
| 161 | device usb 2.9 on end |
| 162 | end |
Karthikeyan Ramasubramanian | cd69259 | 2019-01-28 16:01:13 -0700 | [diff] [blame] | 163 | end |
| 164 | end |
| 165 | end # - XHCI |
Jagadish Krishnamoorthy | 757a246 | 2018-05-17 17:08:51 -0700 | [diff] [blame] | 166 | device pci 15.1 on end # - XDCI |
Furquan Shaikh | 0be087d | 2018-06-24 23:00:13 -0700 | [diff] [blame] | 167 | device pci 16.0 on end # - I2C 0 |
| 168 | device pci 16.1 on end # - I2C 1 |
Furquan Shaikh | 4b95fa2 | 2018-08-10 11:58:54 -0700 | [diff] [blame] | 169 | device pci 16.2 off end # - I2C 2 |
Furquan Shaikh | 7780651 | 2018-10-04 17:55:36 -0700 | [diff] [blame] | 170 | device pci 16.3 off end # - I2C 3 |
Furquan Shaikh | 0be087d | 2018-06-24 23:00:13 -0700 | [diff] [blame] | 171 | device pci 17.0 on end # - I2C 4 |
| 172 | device pci 17.1 on end # - I2C 5 |
| 173 | device pci 17.2 on end # - I2C 6 |
| 174 | device pci 17.3 off end # - I2C 7 |
Shamile Khan | c5f354b | 2018-02-22 13:45:39 -0800 | [diff] [blame] | 175 | device pci 18.0 on end # - UART 0 |
| 176 | device pci 18.1 off end # - UART 1 |
| 177 | device pci 18.2 on end # - UART 2 |
| 178 | device pci 18.3 off end # - UART 3 |
Ravi Sarawadi | c293496 | 2018-02-27 13:57:01 -0800 | [diff] [blame] | 179 | device pci 19.0 on |
| 180 | chip drivers/spi/acpi |
| 181 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 182 | register "compat_string" = ""google,cr50"" |
| 183 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_63_IRQ)" |
| 184 | device spi 0 on end |
| 185 | end |
| 186 | end # - GSPI 0 |
Shamile Khan | c5f354b | 2018-02-22 13:45:39 -0800 | [diff] [blame] | 187 | device pci 19.1 off end # - SPI 1 |
| 188 | device pci 19.2 on end # - SPI 2 |
| 189 | device pci 1a.0 on end # - PWM |
| 190 | device pci 1c.0 on end # - eMMC |
| 191 | device pci 1e.0 off end # - SDIO |
| 192 | device pci 1f.0 on |
| 193 | chip ec/google/chromeec |
| 194 | device pnp 0c09.0 on end |
| 195 | end |
| 196 | end # - ESPI |
| 197 | device pci 1f.1 on end # - SMBUS |
| 198 | end |
John Zhao | 1e6a889 | 2018-11-05 14:45:02 -0800 | [diff] [blame] | 199 | |
| 200 | # FSP provides UPD interface to execute IPC command. PMIC has |
| 201 | # I2C_Slave_Address (31:24): 0x5E, Register_Offset (23:16): 0x43, |
| 202 | # RegOrValue (15:8): 0x2 and RegAndValue (7:0) 0xF8. |
| 203 | # The register is defined as: D[7:3] RSVD, D[2:0] PWROKDELAY. |
| 204 | # uint8 RegOrValue, RegAndValue, PmicReadReg |
| 205 | # RegOrValue = (UINT8)((PmicPmcIpcCtrl >> 8) & 0Xff); |
| 206 | # RegAndValue = (UINT8)(PmicPmcIpcCtrl & 0Xff); |
| 207 | # PmicReadReg &= RegAndValue; |
| 208 | # PmicReadReg |= RegOrValue; |
| 209 | # PmicReadReg value will be programmed into PMIC D[2:0] PWROKDELAY field |
| 210 | # and D[7:3] RSVD will not be impacted. |
| 211 | |
| 212 | # Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay |
| 213 | # from 100ms to 10ms. |
| 214 | # PWROKDELAY[2:0]: 000=2.5ms, 001=5.0ms, 010=10ms, 011=15ms, 100=20ms, |
| 215 | # 101=50ms, 110=75ms, 111=100ms (default) |
| 216 | register "PmicPmcIpcCtrl" = "0x5e4302f8" |
Hannah Williams | 5e83e8b | 2018-02-09 18:35:17 -0800 | [diff] [blame] | 217 | end |