Angel Pons | f5627e8 | 2020-04-05 15:46:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 2 | |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 3 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 4 | #include <device/mmio.h> |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 5 | #include <device/device.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 7 | #include <intelblocks/fast_spi.h> |
Angel Pons | b0f52fb | 2021-03-01 18:11:13 +0100 | [diff] [blame] | 8 | #include <intelblocks/gpio.h> |
Furquan Shaikh | 1876f3a | 2017-12-07 18:39:34 -0800 | [diff] [blame] | 9 | #include <intelblocks/gspi.h> |
Caveh Jalali | 1428f01 | 2018-01-23 22:15:24 -0800 | [diff] [blame] | 10 | #include <intelblocks/lpc_lib.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 11 | #include <intelblocks/p2sb.h> |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 12 | #include <intelblocks/pcr.h> |
Lijian Zhao | 031020e | 2017-12-15 12:58:07 -0800 | [diff] [blame] | 13 | #include <intelblocks/pmclib.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 14 | #include <intelblocks/rtc.h> |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 15 | #include <soc/bootblock.h> |
Subrata Banik | 73b1bd7 | 2019-11-28 13:56:24 +0530 | [diff] [blame] | 16 | #include <soc/gpio.h> |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 17 | #include <soc/iomap.h> |
| 18 | #include <soc/lpc.h> |
| 19 | #include <soc/p2sb.h> |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 20 | #include <soc/pch.h> |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 21 | #include <soc/pci_devs.h> |
| 22 | #include <soc/pcr_ids.h> |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 23 | #include <soc/pm.h> |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 24 | |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 25 | #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP 0x1400 |
| 26 | #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H 0x0980 |
| 27 | |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 28 | #define PCR_PSFX_TO_SHDW_BAR0 0 |
| 29 | #define PCR_PSFX_TO_SHDW_BAR1 0x4 |
| 30 | #define PCR_PSFX_TO_SHDW_BAR2 0x8 |
| 31 | #define PCR_PSFX_TO_SHDW_BAR3 0xC |
| 32 | #define PCR_PSFX_TO_SHDW_BAR4 0x10 |
| 33 | #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 |
| 34 | #define PCR_PSFX_T0_SHDW_PCIEN 0x1C |
| 35 | |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 36 | static uint32_t get_pmc_reg_base(void) |
| 37 | { |
Michael Niewöhner | 89fe2f3 | 2021-01-23 13:57:03 +0100 | [diff] [blame] | 38 | if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 39 | return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H; |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 40 | else |
Michael Niewöhner | 89fe2f3 | 2021-01-23 13:57:03 +0100 | [diff] [blame] | 41 | return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP; |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 42 | } |
| 43 | |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 44 | static void soc_config_pwrmbase(void) |
| 45 | { |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 46 | /* |
| 47 | * Assign Resources to PWRMBASE |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 48 | * Clear BIT 1-2 Command Register |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 49 | */ |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 50 | pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 51 | |
| 52 | /* Program PWRM Base */ |
| 53 | pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); |
| 54 | |
| 55 | /* Enable Bus Master and MMIO Space */ |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 56 | pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 57 | |
| 58 | /* Enable PWRM in PMC */ |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 59 | setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 60 | } |
| 61 | |
| 62 | void bootblock_pch_early_init(void) |
| 63 | { |
Furquan Shaikh | d149bfa | 2020-11-22 20:00:28 -0800 | [diff] [blame] | 64 | /* |
| 65 | * Perform P2SB configuration before any another controller initialization as the |
| 66 | * controller might want to perform PCR settings. |
| 67 | */ |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 68 | p2sb_enable_bar(); |
| 69 | p2sb_configure_hpet(); |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 70 | |
Furquan Shaikh | d149bfa | 2020-11-22 20:00:28 -0800 | [diff] [blame] | 71 | fast_spi_early_init(SPI_BASE_ADDRESS); |
| 72 | gspi_early_bar_init(); |
| 73 | |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 74 | /* |
| 75 | * Enabling PWRM Base for accessing |
| 76 | * Global Reset Cause Register. |
| 77 | */ |
| 78 | soc_config_pwrmbase(); |
| 79 | } |
| 80 | |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 81 | static void soc_config_acpibase(void) |
| 82 | { |
| 83 | uint32_t pmc_reg_value; |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 84 | uint32_t pmc_base_reg; |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 85 | |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 86 | pmc_base_reg = get_pmc_reg_base(); |
| 87 | if (!pmc_base_reg) |
Keith Short | 15588b0 | 2019-05-09 11:40:34 -0600 | [diff] [blame] | 88 | die_with_post_code(POST_HW_INIT_FAILURE, |
| 89 | "Invalid PMC base address\n"); |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 90 | |
| 91 | pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + |
| 92 | PCR_PSFX_TO_SHDW_BAR4); |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 93 | |
| 94 | if (pmc_reg_value != 0xFFFFFFFF) |
| 95 | { |
| 96 | /* Disable Io Space before changing the address */ |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 97 | pcr_rmw32(PID_PSF3, pmc_base_reg + |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 98 | PCR_PSFX_T0_SHDW_PCIEN, |
| 99 | ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); |
| 100 | /* Program ABASE in PSF3 PMC space BAR4*/ |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 101 | pcr_write32(PID_PSF3, pmc_base_reg + |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 102 | PCR_PSFX_TO_SHDW_BAR4, |
| 103 | ACPI_BASE_ADDRESS); |
| 104 | /* Enable IO Space */ |
Maulik V Vaghela | 9b08a18 | 2018-07-17 21:52:27 +0530 | [diff] [blame] | 105 | pcr_rmw32(PID_PSF3, pmc_base_reg + |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 106 | PCR_PSFX_T0_SHDW_PCIEN, |
| 107 | ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); |
| 108 | } |
| 109 | } |
| 110 | |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 111 | void pch_early_iorange_init(void) |
| 112 | { |
Christian Walter | f4aa501 | 2019-08-13 15:09:10 +0200 | [diff] [blame] | 113 | uint16_t io_enables = LPC_IOE_EC_4E_4F | LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | |
Duncan Laurie | 2aef7f3 | 2018-11-17 12:13:59 -0700 | [diff] [blame] | 114 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 115 | |
| 116 | /* IO Decode Range */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 117 | if (CONFIG(DRIVERS_UART_8250IO)) |
Duncan Laurie | 2aef7f3 | 2018-11-17 12:13:59 -0700 | [diff] [blame] | 118 | lpc_io_setup_comm_a_b(); |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 119 | |
| 120 | /* IO Decode Enable */ |
Michael Niewöhner | 33c0aac | 2021-01-24 12:56:12 +0100 | [diff] [blame] | 121 | lpc_enable_fixed_io_ranges(io_enables); |
Caveh Jalali | 1428f01 | 2018-01-23 22:15:24 -0800 | [diff] [blame] | 122 | |
| 123 | /* Program generic IO Decode Range */ |
| 124 | pch_enable_lpc(); |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 125 | } |
| 126 | |
Usha P | 33ff4cc | 2019-11-28 10:05:45 +0530 | [diff] [blame] | 127 | void bootblock_pch_init(void) |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 128 | { |
| 129 | /* |
Angel Pons | b0f52fb | 2021-03-01 18:11:13 +0100 | [diff] [blame] | 130 | * Clear the GPI interrupt status and enable registers. These |
| 131 | * registers do not get reset to default state when booting from S5. |
| 132 | */ |
| 133 | gpi_clear_int_cfg(); |
| 134 | |
| 135 | /* |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 136 | * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, |
| 137 | * GPE0_STS, GPE0_EN registers. |
| 138 | */ |
| 139 | soc_config_acpibase(); |
| 140 | |
Lijian Zhao | 031020e | 2017-12-15 12:58:07 -0800 | [diff] [blame] | 141 | /* Set up GPE configuration */ |
| 142 | pmc_gpe_init(); |
| 143 | |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 144 | enable_rtc_upper_bank(); |
Subrata Banik | 73b1bd7 | 2019-11-28 13:56:24 +0530 | [diff] [blame] | 145 | |
| 146 | /* GPIO community PM configuration */ |
| 147 | soc_gpio_pm_configuration(); |
Andrey Petrov | f35804b | 2017-06-05 13:22:41 -0700 | [diff] [blame] | 148 | } |