Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Arthur Heymans | e48dcb7 | 2022-05-31 21:48:15 +0200 | [diff] [blame] | 3 | #include <cpu/x86/mtrr.h> |
| 4 | #include <cpu/x86/mp.h> |
| 5 | #include <amdblocks/cpu.h> |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 6 | #include <amdblocks/smm.h> |
| 7 | #include <console/console.h> |
| 8 | #include <cpu/amd/amd64_save_state.h> |
Grzegorz Bernacki | d34dbe5 | 2023-04-25 15:30:14 +0000 | [diff] [blame] | 9 | #include <cpu/amd/microcode.h> |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 10 | #include <cpu/amd/msr.h> |
Arthur Heymans | e48dcb7 | 2022-05-31 21:48:15 +0200 | [diff] [blame] | 11 | #include <cpu/amd/mtrr.h> |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 12 | #include <cpu/cpu.h> |
| 13 | #include <cpu/x86/msr.h> |
| 14 | #include <cpu/x86/smm.h> |
| 15 | #include <types.h> |
| 16 | |
Arthur Heymans | e48dcb7 | 2022-05-31 21:48:15 +0200 | [diff] [blame] | 17 | /* AP MTRRs will be synced to the BSP in the SIPI vector so set them up before MP init. */ |
| 18 | static void pre_mp_init(void) |
| 19 | { |
| 20 | const msr_t syscfg = rdmsr(SYSCFG_MSR); |
| 21 | if (syscfg.lo & SYSCFG_MSR_TOM2WB) |
| 22 | x86_setup_mtrrs_with_detect_no_above_4gb(); |
| 23 | else |
| 24 | x86_setup_mtrrs_with_detect(); |
| 25 | x86_mtrr_check(); |
Grzegorz Bernacki | d34dbe5 | 2023-04-25 15:30:14 +0000 | [diff] [blame] | 26 | if (CONFIG(SOC_AMD_COMMON_BLOCK_UCODE)) |
| 27 | amd_load_microcode_from_cbfs(); |
Arthur Heymans | e48dcb7 | 2022-05-31 21:48:15 +0200 | [diff] [blame] | 28 | } |
| 29 | |
| 30 | static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, |
| 31 | size_t *smm_save_state_size) |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 32 | { |
Arthur Heymans | 8cd1dfa | 2022-05-31 22:00:13 +0200 | [diff] [blame] | 33 | printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); |
| 34 | |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 35 | uintptr_t tseg_base; |
| 36 | size_t tseg_size; |
| 37 | |
| 38 | smm_region(&tseg_base, &tseg_size); |
| 39 | |
Arthur Heymans | 8cd1dfa | 2022-05-31 22:00:13 +0200 | [diff] [blame] | 40 | if (!IS_ALIGNED(tseg_base, tseg_size)) { |
| 41 | printk(BIOS_ERR, "TSEG base not aligned to TSEG size\n"); |
| 42 | return; |
| 43 | } |
| 44 | /* Minimum granularity for TSEG MSRs */ |
| 45 | if (tseg_size < 128 * KiB) { |
| 46 | printk(BIOS_ERR, "TSEG size (0x%zx) too small\n", tseg_size); |
| 47 | return; |
| 48 | } |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 49 | |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 50 | |
| 51 | smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); |
| 52 | *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); |
| 53 | } |
| 54 | |
Arthur Heymans | 43ed5d2 | 2022-05-31 21:50:51 +0200 | [diff] [blame] | 55 | static void tseg_valid(void) |
| 56 | { |
| 57 | msr_t mask = rdmsr(SMM_MASK_MSR); |
| 58 | mask.lo |= SMM_TSEG_VALID; |
| 59 | |
| 60 | wrmsr(SMM_MASK_MSR, mask); |
| 61 | } |
| 62 | |
Arthur Heymans | 56776a1 | 2022-05-19 11:31:10 +0200 | [diff] [blame] | 63 | static void smm_relocation_handler(void) |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 64 | { |
Arthur Heymans | 8cd1dfa | 2022-05-31 22:00:13 +0200 | [diff] [blame] | 65 | uintptr_t tseg_base; |
| 66 | size_t tseg_size; |
| 67 | |
Felix Held | 89ca478 | 2023-09-12 15:01:02 +0200 | [diff] [blame^] | 68 | /* For the TSEG masks all physical address bits including the ones reserved for memory |
| 69 | encryption need to be taken into account. TODO: Find out why this is the case */ |
| 70 | const unsigned int total_physical_address_bits = |
| 71 | cpu_phys_address_size() + get_reserved_phys_addr_bits(); |
| 72 | |
Arthur Heymans | 8cd1dfa | 2022-05-31 22:00:13 +0200 | [diff] [blame] | 73 | smm_region(&tseg_base, &tseg_size); |
| 74 | |
| 75 | msr_t msr; |
Felix Held | cabf6ea | 2023-03-09 19:43:18 +0100 | [diff] [blame] | 76 | msr.raw = tseg_base; |
Arthur Heymans | 8cd1dfa | 2022-05-31 22:00:13 +0200 | [diff] [blame] | 77 | wrmsr(SMM_ADDR_MSR, msr); |
| 78 | |
| 79 | msr.lo = ~(tseg_size - 1); |
| 80 | msr.lo |= SMM_TSEG_WB; |
Felix Held | 89ca478 | 2023-09-12 15:01:02 +0200 | [diff] [blame^] | 81 | msr.hi = (1 << (total_physical_address_bits - 32)) - 1; |
Arthur Heymans | 8cd1dfa | 2022-05-31 22:00:13 +0200 | [diff] [blame] | 82 | wrmsr(SMM_MASK_MSR, msr); |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 83 | |
Arthur Heymans | 56776a1 | 2022-05-19 11:31:10 +0200 | [diff] [blame] | 84 | uintptr_t smbase = smm_get_cpu_smbase(cpu_index()); |
| 85 | msr_t smm_base = { |
Felix Held | cabf6ea | 2023-03-09 19:43:18 +0100 | [diff] [blame] | 86 | .raw = smbase |
Arthur Heymans | 56776a1 | 2022-05-19 11:31:10 +0200 | [diff] [blame] | 87 | }; |
| 88 | wrmsr(SMM_BASE_MSR, smm_base); |
Arthur Heymans | 43ed5d2 | 2022-05-31 21:50:51 +0200 | [diff] [blame] | 89 | |
| 90 | tseg_valid(); |
| 91 | lock_smm(); |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 92 | } |
Arthur Heymans | e48dcb7 | 2022-05-31 21:48:15 +0200 | [diff] [blame] | 93 | |
Grzegorz Bernacki | d34dbe5 | 2023-04-25 15:30:14 +0000 | [diff] [blame] | 94 | static void post_mp_init(void) |
| 95 | { |
| 96 | if (CONFIG(SOC_AMD_COMMON_BLOCK_UCODE)) |
| 97 | amd_free_microcode(); |
| 98 | global_smi_enable(); |
| 99 | } |
| 100 | |
Arthur Heymans | e48dcb7 | 2022-05-31 21:48:15 +0200 | [diff] [blame] | 101 | const struct mp_ops amd_mp_ops_with_smm = { |
| 102 | .pre_mp_init = pre_mp_init, |
| 103 | .get_cpu_count = get_cpu_count, |
| 104 | .get_smm_info = get_smm_info, |
Arthur Heymans | 56776a1 | 2022-05-19 11:31:10 +0200 | [diff] [blame] | 105 | .per_cpu_smm_trigger = smm_relocation_handler, |
Grzegorz Bernacki | d34dbe5 | 2023-04-25 15:30:14 +0000 | [diff] [blame] | 106 | .post_mp_init = post_mp_init, |
Arthur Heymans | e48dcb7 | 2022-05-31 21:48:15 +0200 | [diff] [blame] | 107 | }; |
Arthur Heymans | 4fcaccf | 2022-06-02 13:17:37 +0200 | [diff] [blame] | 108 | |
| 109 | const struct mp_ops amd_mp_ops_no_smm = { |
| 110 | .pre_mp_init = pre_mp_init, |
| 111 | .get_cpu_count = get_cpu_count, |
| 112 | }; |